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1 7632a?mp3?03/06 features ? audio processor ? proprietary digital signal processor ? mp3 (full mpeg i/ii-layer 3) decoder (1) ? windows media ? audio (wma) decoder (1) ? ogg (vorbis) decoder (2) ? wav pcm decoder/encoder ? adpcm decoder/encoder (g726: 40, 32, 24, 16 kbps) ? audio codec ? 16-bit stereo d/a converters (3) ? headphone amplifier with analog volume control (3) ? microphone pre-amplifier with bias control ? 16-bit mono a/d converter: microphone or line inputs recording ? stereo lines input for fm playback or mono recording ? baseband sound processor with digital volume control, bass, medium, and treble control, bass boost and virtual surround effects ? digital audio dac interface ?pcm / i 2 s format compatible ? usb rev 2.0 controller ? high speed mode (480 mbps) ? full speed mode (12 mbps) ? on the go full speed mode ? data flow controller ? 16-bit multimedia bus with 2 dma channels for high speed transfer with usb ? nand flash controller ? up to four memories with page size: 512b, 1kb, 2kb or 4kb ? built-in ecc and hardware write protection ? xd-picture card? and smartmedia ? card interface ? multimediacard ? controller ? multimediacard 1-bit / 4-bits modes (v4.0 compatible) ? secure digital card 1-bit / 4-bit modes ? man machine interface ? glueless generic lcd interface ? keyboard interface ? remote controlled / streaming ? psi i80 slave interface (ebi compatible) up to 6mbyte/s ? spi master and slave modes ? full duplex uart with baud rate generator up to 6 mbit/s (rx, tx, rts, cts) ? control processor ? enhanced 8-bit mcu c51 core (f max = 24 mhz) ? 64k bytes of internal ram for application code and data ? boot rom memory: secured nand flash boot strap (standard), usb boot loader ? two 16-bit timers/counters ? hardware watchdog timer ? power management ? 1.8v 40 ma single aaa or aa battery powered (4) ? direct usb v bus supply ? 3v - 50 ma regulator output ? 1.8v - 50 ma regulator output ? battery voltage monitoring ? power-on reset ? software programmable mcu clock ? idle, power-down, power-off modes ? on chip debug ? operating conditions ? supply 0.9v to 5v ? 25 ma typical operating at 25c (estimation to be confirmed) ? temperature range: -40c to +85c single-chip digital audio decoder - encoder with usb 2.0 interface AT85C51SND3b1 AT85C51SND3b2 AT85C51SND3b3 preliminary
2 AT85C51SND3bx 7632a?mp3?03/06 ? packages ? lqfp100, bga100, dice notes: 1. see ordering information 2. future product 3. AT85C51SND3b2 & AT85C51SND3b3 only 4. AT85C51SND3b3 only description digital music players, mobile phones need ready to use low-cost solutions for very fast time to market. the AT85C51SND3bx with associated firmware embeds in a single chip all features, hardware and software, for digital music players, mobile phones and car audio systems: mp3 decoder, wma decoder, display interface, serial interface, parallel interface, usb high speed and usb host. close to a plug and play solution for most applications, the AT85C51SND3bx drastically reduces system development for the best time to market. the AT85C51SND3bx han - dles full file system management with nand flash and flash cards, including full detection and operation of a thumb drive. the AT85C51SND3a is used either as a mas - ter controller, or as a slave controller interfacing easily with most of the base-band or host processors available on the market. in addition to the mp3 and wma format, the AT85C51SND3bx associated firmware will also later support, the ogg format, basic midi features for low cost mobile phones and jpeg still pictures decoding . the AT85C51SND3b is ideally fitting mass production markets. the AT85C51SND3bx includes power management with: 5v usb v bus direct supply, 2.7v to 3.6v supply, 1.8v supply or alkaline battery supply (0.9v to 1.8v). external nand flash or flash card can be supplied by the AT85C51SND3b at 1.8v or 3v. the AT85C51SND3bx supports many applications including: mobile phones, music players, portable navigation, car audio, music in shopping centers, applications includ - ing mmc/sd flash cards in industrial applications. to facilitate custom applications with the AT85C51SND3bx, a development kit at85dvk-07 is available with hardware and firmware database. key features ? firmware to support ?mp3 ?wma ? adpcm/wav voice or line recording ? and coming soon ogg, midi and jpeg decoder ? audio codec ? internal dac ? fm inputs ? memory support ? up to 4x nand-flash ? sd/mmc cards ?usb ? high speed, full speed ? otg (reduced host)
3 AT85C51SND3bx 7632a?mp3?03/06 block diagram figure 1. AT85C51SND3bx block diagram notes: 1. AT85C51SND3b3 only 2. AT85C51SND3b2 & AT85C51SND3b3 only audio dac interface baseband processor audio processor audio codec (2) audio controller power management clock controller memory controllers nand flash sm / xd cards oscillator pll clock generator usb controller hs / fs device host / otg controller control processor unit enhanced x2 c51 core remote interfaces mmc v4 sd cards 1.8v dc-dc (1) 3v regulator 1.8v regulator mmi controller keyboard interface lcd interface serial peripheral interface serial i/o interface power fail detector parallel slave interface debug unit on chip debug memory unit configurable 64 kbytes code / data ram boot rom 16-bit multimedia bus multimedia bus manager data flow controller controller AT85C51SND3bx timer unit 2 x 16-bit timers watchdog timer interrupt controller
4 AT85C51SND3bx 7632a?mp3?03/06 application information the AT85C51SND3bx allow design of 2 typical applications which differentiate by the power supply voltage: ? the very low voltage system the player operates at 1.8v and allows very low power consumption. ? the low voltage system the player operates at 3v and allows low power consumption. very low voltage 1.8v system figure 2. typical very low voltage 1.8v application 1.8v nf memories pa sd/mmc battery fm module AT85C51SND3b3 lvdd write protect lcd
5 AT85C51SND3bx 7632a?mp3?03/06 low voltage 3v system figure 3. typical low voltage 3v application 3v nf memories sd/mmc 3v dc-dc battery fm module AT85C51SND3b2 hvdd write protect lcd
6 AT85C51SND3bx 7632a?mp3?03/06 pin description pinouts figure 4. AT85C51SND3bx 100-pin qfp package notes: 1. leave these pins unconnected for AT85C51SND3b1 & AT85C51SND3b2 products 2. leave these pins unconnected for AT85C51SND3b1 product nfd5 nfd6 nfd7 p0.1/sd1/ld1 p0.0/sd0/ld0 p0.2/sd2/ld2 p3.1/txd/mosi p3.2/int0 /rts /sck p3.3/int1 /cts /ss p3.4/t0 nfd3 nfd4 p5.3/swr /lwr /lrw p5.2/sa0/la0/lrs AT85C51SND3bx micin linr linl avcm micbias 1 2 3 4 5 6 7 8 13 11 10 p1.4 cvss p3.6/uvcon p3.7/uid ulvdd dmf avss1 9 12 14 15 16 apvdd x2 x1 apvss avss2 avdd2 outl (2) outr (2) aref avdd1 p1.1/kin1 p1.0/kin0 bvdd dcpwr (1) bvss dcli (1) rlvdd vss uvcc hvdd lvdd (1) 17 18 19 20 26 27 28 33 31 30 29 32 34 35 36 37 38 39 40 53 51 52 54 55 56 57 58 59 60 81 82 83 84 85 86 87 88 93 91 90 89 92 94 95 96 97 98 99 100 p1.3/kin3 p1.2/kin2 dpf uvss upvss upvdd ocdr ocdt/isp uhvdd dph dmh uvss ubias 21 22 23 24 25 41 42 43 48 46 45 44 47 49 50 63 61 62 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p4.1/dclk p4.2/ddat p4.3/dsel rst p4.0/oclk nfd2 p5.1/scs /lcs p5.0/srd /lrd /lde p0.3/sd3/ld3 p0.4/sd4/ld4 p0.5/sd5/ld5 p0.6/sd6/ld6 p0.7/sd7/ld7 iovss iovdd p3.0/rxd/miso p1.6 p1.7 p2.0/sdins p2.1/sdlck p2.2/sdcmd p2.3/sdclk p2.4/sddat0 iovdd nfwp p1.5 p2.5/sddat1 p2.6/sddat2 p2.7/sddat3 iovss nfce0 p4.4/nfce1 /smlck nfwe nfale nfcle p4.6/nfce3 /smce p4.5/nfce2 /smins nfd1 nfd0 nfre
7 AT85C51SND3bx 7632a?mp3?03/06 signals description system table 1. system signal description table 2. ports signal description signal name type description alternate function rst i/o reset input holding this pin low for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-up resistor (r rst ) which allows the device to be reset by connecting a capacitor between this pin and v ss . asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. in order to reset external components connected to the rst line a low level 96-clock period pulse is generated when the watchdog timer reaches its time-out period. - isp i in system programming assert this pin during reset phase to enter the in system programming mode. ocdt signal name type description alternate function p0.7:0 i/o port 0 p0 is an 8-bit bidirectional i/o port with internal pull-ups. ld7:0 p1.7:0 i/o port 1 p1 is an 8-bit bidirectional i/o port with internal pull-ups. kin3:0 p2.7:0 i/o port 2 p2 is an 8-bit bidirectional i/o port with internal pull-ups. sdins sdlck sdcmd sdclk sddat3:0 p3.4:0 p3.7:6 i/o port 3 p3 is a 7-bit bidirectional i/o port with internal pull-ups. rxd miso txd mosi int0 rts sck int1 cts ss t0 uvcon uid
8 AT85C51SND3bx 7632a?mp3?03/06 table 3. timer 0 and timer 1 signal description p4.6:0 i/o port 4 p4 is a 7-bit bidirectional i/o port with internal pull-ups. oclk dclk ddat dsel nfce1 / smlck nfce2 / smins nfce3 / smce p5.3:0 i/o port 5 p5 is a 4-bit bidirectional i/o port with internal pull-ups. lrd /lde sdr lcs scs la0/lrs sa0 lwr /lrw swr signal name type description alternate function int0 i timer 0 gate input int0 serves as external run control for timer 0, when selected by gate0 bit in tcon register. external interrupt 0 int0 input sets ie0 in the tcon register. if bit it0 in this register is set, bit ie0 is set by a falling edge on int0 . if bit it0 is cleared, bit ie0 is set by a low level on int0 . p3.2 rts sck int1 i timer 1 gate input int1 serves as external run control for timer 1, when selected by gate1 bit in tcon register. external interrupt 1 int1 input sets ie1 in the tcon register. if bit it1 in this register is set, bit ie1 is set by a falling edge on int1 . if bit it1 is cleared, bit ie1 is set by a low level on int1 . p3.3 cts ss t0 i timer 0 external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. p3.4 signal name type description alternate function
9 AT85C51SND3bx 7632a?mp3?03/06 clock controller table 4. clock signal description memory controllers table 5. secure digital card / mutimediacard controller signal description table 6. nand flash / smartmedia card controller signal description signal name type description alternate function x1 i input of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. x1 is the clock source for internal timing. - x2 o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave x2 unconnected. - upvdd pwr usb pll supply voltage connect this pin to lvdd pin. - upvss gnd usb pll circuit ground connect this pin to lvss pin. - apvdd pwr audio pll supply voltage connect this pin to lvdd pin. - apvss gnd audio pll circuit ground connect this pin to lvss pin. - signal name type description alternate function sdclk o sd/mmc clock data or command clock transfer. p2.3 sdcmd i/o sd/mmc command line bidirectional command line used for commands and responses transfer. p2.2 sddat3:0 i/o sd/mmc data lines bidirectional data lines. in 1-bit mode configuration sddat0 is the dat signal and sddat3:1 are not used and can be reused as i/o ports. p2.7:4 sdins i sd/mmc card insertion signal sdins is the card presence signal. a low level on this input indicates the card is present in its slot. note: this signal is generated by the sd/mmc card connector. p2.0 sdlck i sd card write lock signal sdlck is the sd card write protected input. a low level on this pin indicates the card is write protected. note: this signal is generated by the sd/mmc card connector. p2.1 signal name type description alternate function nfd7:0 i/o memory data bus 8-bit bidirectional data bus. - nfale o address latch enable signal asserted high during address write cycle. -
10 AT85C51SND3bx 7632a?mp3?03/06 usb controller table 7. usb controller signal description nfcle o command latch enable signal asserted high during command write cycle. - nfre o read enable signal read signal asserted low during nf/smc read operation. - nfwe o write enable signal write signal asserted low during nf/smc write operation. - nfce0 o nand flash 0 chip enable nfce0 is active low and is asserted by the nand flash controller each time it makes access to the device 0. - nfce1 smlck o i nand flash 1 chip enable nfce1 is active low and is asserted by the nand flash controller each time it makes access to the selected device. smartmediacard/xd-picture card write lock signal smlck is the card write protected input. a low level on this pin indicates the card is write protected. note: when used as smlck input, pad has internal pull-up. p4.4 nfce2 smins o i nand flash 2 chip enable nfce2 is active low and is asserted by the nand flash controller each time it makes access to the selected device. smartmediacard/xd-picture card insertion signal smins is the card presence signal. a low level on this input indicates the card is present in its slot. note: when used as smins input, pad has internal pull-up. p4.5 nfce3 smce o nand flash 3 chip enable nfce3 is active low and is asserted by the nand flash controller each time it makes access to the selected device. smartmediacard/xd-picture card chip enable smce is active low and is asserted by the nand flash controller each time it makes access to the card. p4.6 nfwp o write protect signal nfwp is the nand flash / smartmediacard/xd-picture card write protect signal. this signal is active low and is set to low during reset in order to protect the memory against parasitic writes. - signal name type description alternate function signal name type description alternate function dpf i/o usb full speed positive data upstream port - dmf i/o usb full speed minus data upstream port - dph i/o usb high speed plus data upstream port - dmh i/o usb high speed minus data upstream port - uvcon o usb vbus control line uvcon is used to control the external vbus power supply on or off. note: this output is requested for otg mode. p3.6
11 AT85C51SND3bx 7632a?mp3?03/06 audio processor table 8. i2s output description table 9. audio codec description uid i usb otg identifier input this pin monitors the function of the otg device. note: this input is requested for otg mode. p3.7 uvcc pwr usb supply voltage connect this pin to usb v bus power line. - ulvdd pwr usb pad low voltage connect this pin to lvdd pin. - uhvdd pwr usb pad high voltage connect this pin to hvdd pin. - uvss gnd usb ground - ubias o usb bias connect this pin to external resistor and capacitor. signal name type description alternate function signal name type description alternate function oclk o over-sampling clock line p4.0 dclk o data clock line p4.1 ddat o data lines p4.2 dsel o data channel selection line p4.3 signal name type description alternate function linr i right channel analog input - linl i left channel analog input - micin i electret microphone analog input - micbias o electret microphone bias output - outr o right channel output do not connect on AT85C51SND3b1 product - outl o left channel output do not connect on AT85C51SND3b1 product - avcm i analog common mode voltage connect this pin to external decoupling capacitor. - aref o analog reference voltage connect this pin to external decoupling capacitor. - avdd1 pwr analog power supply 1 connect this pin to lvdd pin. - avss1 gnd analog ground 1 connect this pin to lvss pin. -
12 AT85C51SND3bx 7632a?mp3?03/06 parallel slave interface table 10. psi signal description serial interfaces table 11. spi controller signal description table 12. sio signal description avdd2 pwr analog power supply 2 low voltage system: connect this pin to lvdd pin. high voltage system: connect this pin to external +3v power supply. - avss2 gnd analog ground 2 low voltage system: connect this pin to lvss pin. high voltage system: connect this pin to external +3v ground. - signal name type description alternate function signal name type description alternate function sd7:0 i/o slave data bus 8-bit bidirectional data bus. p0.7:0 ld7:0 srd i slave read signal read signal asserted low during external host read operation. p5.0 lrd /lde swr i slave write signal write signal asserted low during external host write operation. p5.3 lwr /lrw scs i slave chip select select signal asserted low during external host read or write operation. p5.1 lcs sa0 i slave address bit 0 address signal asserted during external host read or write operation. p5.2 la0/lrs signal name type description alternate function miso i/o spi master input slave output data line when in master mode, miso receives data from the slave peripheral. when in slave mode, miso outputs data to the master controller. p3.0 rxd mosi i/o spi master output slave input data line when in master mode, mosi outputs data to the slave peripheral. when in slave mode, mosi receives data from the master controller. p3.1 txd sck i/o spi clock line when in master mode, sck outputs clock to the slave peripheral. when in slave mode, sck receives clock from the master controller. p3.2 int0 rts ss i spi slave select line when in controlled slave mode, ss enables the slave mode. p3.3 int1 cts signal name type description alternate function rxd i/o receive serial data rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2 and 3. p3.0 miso
13 AT85C51SND3bx 7632a?mp3?03/06 mmi interface table 13. keypad controller signal description table 14. lcd interface signal description power management table 15. power signal description txd o transmit serial data txd outputs the shift clock in serial i/o mode 0 and transmits data in serial i/o modes 1, 2 and 3. p3.1 mosi rts o request to send hardware handshake line asserted low by hardware when sio is ready to receive data. p3.2 int0 sck cts i clear to send hardware handshake line asserted low by external hardware when sio is allowed to send data. p3.3 int1 ss signal name type description alternate function signal name type description alternate function kin3:0 i keypad input lines holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. p1.3:0 signal name type description alternate function ld7:0 i/o display data bus 8-bit bidirectional data bus. p0.7:0 sd7:0 lrd /lde o read signal/enable signal 8080: read signal asserted low during display read access. 6800: enable signal asserted high during display access. p5.0 srd lwr /lrw o write signal/read write signal 8080: write signal asserted low during display write access. 6800: read/write signal asserted low/high during display read/write access p5.3 swr lcs o display chip select select signal asserted low during display access. p5.1 scs la0/lrs o display address bit 0/register select address signal asserted during display access. p5.2 sa0 signal name type description alternate function dcpwr i dc-dc power on input connect dcpwr to v ss to start the dc-dc converter. - dcli pwr dc-dc inductance input connect low esr inductance to dcli and bvdd. bvdd pwr battery supply voltage connect this pin to the positive pin of the battery. -
14 AT85C51SND3bx 7632a?mp3?03/06 ocd interface table 16. ocd signal description bvss gnd battery ground connect this pin to the negative pin of the battery. - lvdd pwr low voltage dc-dc power supply output this pin outputs +1.8v typ. from internal dc-dc (battery powered). - rlvdd pwr low voltage regulator power supply output this pin outputs +1.8v typ. from internal regulator (usb powered or +3v external power supply). connect this pin to lvdd incase of internal dc-dc usage. - hvdd pwr high voltage power supply this pin outputs +3v typ. from internal regulator (usb powered). connect this pin to +3v external power supply. - vss gnd power ground connect this pin to the system ground. - cvss gnd core ground connect this pin to vss pin. - iovdd pwr input/output supply voltage connect this pin to lvdd or hvdd pin. - iovss gnd input/output circuit ground connect this pin to vss pin. - signal name type description alternate function signal name type description alternate function ocdr i on chip debug receive input ocdr receives data. - ocdt i/o on chip debug transmit output ocdt transmits data. isp
15 AT85C51SND3bx 7632a?mp3?03/06 internal pin structure table 17. detailed internal pin structure circuit (1) type pins input/output rst input/output p0.7:0 p1.7:0 p2.7:0 p3.5:0 p4.6:0 p5.3:0 ocdt input/output p3.7:6 input kin3:0 sdins sdlck smins smlck tst isp uid int0 int1 t0 rxd ocdr input swr sa0 srd scs ss input/output nfd7:0 sd7:0 ld7:0 sdcmd sddat3:0 miso mosi r rst iovss n iovdd n ps iovdd iovdd 2 osc latch output periods pm pw iovdd iovss n ps hvdd hvdd 2 osc latch output periods pm pw hvdd iovss pm pw iovss iovdd iovdd n p iovss iovdd
16 AT85C51SND3bx 7632a?mp3?03/06 output sdclk sck nfce3:0 nfcle nfale nfwe nfre nfwp smce dsel ddat dclk oclk lwr /le la0/lrs lrd /lrw lcs uvcon txd input/output dpf dmf input/output dph dmh input dcpwr (2) - dcli (2) circuit (1) type pins n p iovss iovdd dpf dmf dph dmh bvdd r dcp n p cvss lvdd
17 AT85C51SND3bx 7632a?mp3?03/06 notes: 1. for information on resistor value, input/output levels, and drive capability, refer to section ?dc characteristics?, page 241. 2. AT85C51SND3b3 only 3. AT85C51SND3b2 & AT85C51SND3b3 only output micbias input micin linr linl output outr (2) outl (2) circuit (1) type pins - + avss avss - +
18 AT85C51SND3bx 7632a?mp3?03/06 power management the power management implements all the internal power circuitry (regulators, links?) as well as power failure detector and reset circuitry. power supply the AT85C51SND3b3 embeds the regulators and a dc to dc step-up convertor to be able to operate from either usb power supply (5v nominal) or from a single cell battery such as aaa battery. the AT85C51SND3b1 and AT85C51SND3b2 embed the regulators to be able to oper - ate from either usb power supply (5v nominal) or from an external 3 volts supply. figure 5. power supply diagram note: 1. external connection mandatory when 1.8v dc-dc is used. regulators the high voltage regulator supplies power to the external devices through hvdd power pin. its nominal voltage output is 3v. the low voltage regulator supplies power to the internal device and external devices through rlvdd power pin. its nominal voltage output is 1.8v. figure 6 shows how to connect external components, capacitors value along with power characteristics are specified in the section ?dc characteristics?. hvdet psta.6 lvdd dcpwr uvcc uvss dcen pcon.3 dcli hvdd vss bvdd bvss rlvdd uvdet psta.7 3 v regulator 1.8 v dc-dc battery monitor 1.8 v regulator vbat optional connection (1) dcpbst pcon.5 to internal core
19 AT85C51SND3bx 7632a?mp3?03/06 schematic figure 6. regulator connection note: depending on power supply scheme, c lv may replace c dc capacitor (see figure 8 ). low voltage dc-dc in AT85C51SND3b3 the low voltage output dc-dc converter supplies power to the internal device and external devices through lvdd power pin. it operates from a single aaa battery. its nominal voltage output is 1.8v. dc-dc start-up dc-dc start-up is done by asserting the dcpwr input until the voltage reaches its nominal value (see section ?power fail detector? ) and firmware starts execution and sets the dcen bit in pcon to maintain the dc-dc enabled. dcpwr input can then be released. as shown in figure 8 dcpwr input is asserted by pressing a key connected to bvss. figure 7. dc-dc start-up phase dc-dc shut-down dc-dc shut-down is done by two different ways: ? clearing the dcen bit while dcpwr pin is de-asserted ? detecting the presence of an internal or external 3v supply, e.g. when the device is connected to usb, dc-dc is disabled to save battery power (1) . note: 1. if dcen bit is left set, the dc-dc will restart as soon as the usb power supply disappears. dc-dc connection figure 8 shows how to connect external components, inductance and components value along with power characteristics are specified in the section ?dc characteristics?. figure 8. battery dc-dc connection note: depending on power supply scheme, c dc1 may replace c lv capacitor (see figure 6 ). hvdd c hv vss rlvdd c lv ( * ) vss dcpwr dcen dc-dc start-up lvdd firmware start-up dc-dc on dc-dc off lvdd bvdd bvss battery l dc dcli c dc1 ( * ) vss rlvdd cvss c dc2 dcpwr
20 AT85C51SND3bx 7632a?mp3?03/06 battery voltage monitor the battery voltage monitor is a 5-bit / 50 mv resolution a to d converter with fixed con - version range as detailed in table 18 . table 18. battery voltage value conversion management the battery voltage monitor is turned on by setting the vbpen and vbcen bits in pcon (see table 20 ). vbpen bit is set first and vbcen bit is set 1 ms later. an addi - tional delay of 16 cycles is required before lauching any conversion. launching a conversion is done by setting vben bit in vbat (see table 22 ). vben is automatically cleared at the end of the conversion which takes 34 clock periods. at this step two cases occur: ? voltage is valid (inside conversion range) vberr is cleared and conversion value is set in vb4:0 according to table 18 . ? voltage is invalid (out of conversion range) vberr is set and value reported by vb4:0 is indeterminate. power reduction mode two power reduction modes are implemented in the AT85C51SND3b: the idle mode and the power-down mode. these modes are detailed in the following sections. in addi - tion to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the x2 mode as detailed in section ?x2 feature?, page 30 . lock mode in order to allow firmware to efficiently enter in idle mode and not to lose any events that should come from one or more interrupts, power reduction modes entry are conditioned to an hardware bit: pmlck in pcon. pmlck is set by software in each isr that needs to report an ev ent to the system and thus disables entry in power reduction mode and allows immediate processing of this event. it is cleared by software after exiting power reduction mode. as shown in figure 9 , when power reduction modes are di sabled by setting pmlck, idl and pd bits in pcon can not be set and idle or power down modes are not entered. figure 9. power reduction controller block diagram vb4:0 battery voltage (v) 00000 [0.9 - 0.95[ 00001 [0.95 - 1.0[ 00010 [1.0 - 1.05[ ? ? 01110 [1.6 - 1.65[ 01111 [1.65 - 1.7[ 10000 [1.7 - 1.75[ system idle system power down idl pcon.0 pd pcon.1 pmlck pcon.2 write to idl write to pd
21 AT85C51SND3bx 7632a?mp3?03/06 idle mode idle mode is a power reduction mode that reduces the power consumption. in this mode, program execution halts. idle mode freezes the clock to the cpu at known states while the peripherals continue to be clocked (refer to section ?system clock generator?, page 29 ). the cpu status before entering idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of idle mode. the contents of the sfrs and ram are also retained. entering idle mode to enter idle mode, the user must set the idl bit in pcon register while pmlck is cleared. the AT85C51SND3b enters idle mode upon execution of the instruction that sets idl bit. the instruction that sets idl bit is the last instruction executed. note: if idl bit and pd bit are set simultaneously, the AT85C51SND3b enter power-down mode. then it does not go in idle mode when exiting power-down mode. exiting idle mode there are 2 ways to exit idle mode: 1. generate an enabled interrupt. ? hardware clears idl bit in pcon register which restores the clock to the cpu. execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated idle mode. the general- purpose flags (gf1 and gf0 in pcon register) may be used to indicate whether an interrupt occurred during nor mal operation or during idle mode. when idle mode is exited by an interrupt, the interrupt service routine may examine gf1 and gf0. 2. generate a reset. ? a logic high on the rst pin clears idl bit in pcon register directly and asynchronously. this restores the clock to the cpu. program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the AT85C51SND3b and vectors the cpu to address 0000h. note: during the time that execution resumes, the internal ram cannot be accessed; however, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external ram. power-down mode the power-down mode places the AT85C51SND3b in a very low power state. power- down mode stops the oscillator and freezes all clocks at known states (refer to the section ?oscillator?, page 27 ). the cpu status prior to entering power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of power-down mode. in addition, the sfrs and ram contents are preserved. entering power-down mode to enter power-down mode, set pd bit in pcon register while pmlck is cleared. the AT85C51SND3b enters the power-down mode upon execution of the instruction that sets pd bit. the instruction that sets pd bit is the last instruction executed. exiting power-down mode there are 2 ways to exit the power-down mode: 1. generate an enabled external interrupt. ? the AT85C51SND3b provides capability to exit from power-down using int0 , int1 , and kin3:0 inputs. in addition, using kin input provides high or low level exit capability (see section ?keyboard interface?, page 239). hardware clears pd bit in pcon register which starts the oscillator and restores
22 AT85C51SND3bx 7632a?mp3?03/06 the clocks to the cpu and peripherals. using intn input, execution resumes when the input is released (see figure 10) while using kinx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see figure 11). this behavior is necessary for decoding the key while it is still pressed. in both cases, execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated power- down mode. note: 1. the external interrupt used to exit power-down mode must be configured as level sensitive ( int0 and int1 ) and must be assigned the highest priority. in addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. the execution will only resume when the interrupt is de-asserted. 2. exit from power-down by external interrupt does not affect the sfrs nor the internal ram content. figure 10. power-down exit waveform using int1:0 figure 11. power-down exit waveform using kin3:0 note: 1. kin3:0 can be high or low-level triggered. 2. generate a reset. ? a logic high on the rst pin clears pd bit in pcon register directly and asynchronously. this starts the oscillator and restores the clock to the cpu and peripherals. program execution momentarily resumes with the instruction immediately following the instruction that activated power-down mode and may continue for a number of clock cycles befo re the internal reset algorithm takes control. reset initializes the AT85C51SND3b and vectors the cpu to address 0000h. notes: 1. during the time that execution resumes, the internal ram cannot be accessed; how- ever, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated the power-down mode should not write to a port pin or to the external ram. 2. exit from power-down by reset redefines all the sfrs, but does not affect the internal ram content. int1:0 osc power-down phase oscillator restart phase active phase active phase kin3:0 (1) osc power-down phase 42000 clock count active phase active phase
23 AT85C51SND3bx 7632a?mp3?03/06 reset in order to secure the product functionality while in power-up or power-down phase or while in running phase, a number of internal mechanisms have been implemented. these mechanisms are listed below and detailed in the following paragraphs. ? external rst input ? power fail detector (brown-out) ? watchdog timer ? pads control figure 12 details the internal reset circuitry. reset source reporting in order for the firmware to take specific actions depending on the source which has cur - rently reset the device, activated reset source is reported to the cpu by extrst, wdtrst, and pfdrst flags in psta register. figure 12. internal reset circuitry pads level control as soon as one reset source is asserted, the pads go to their reset value. this ensures that pads level is steady during reset (e.g. nfwp set to low level and then protecting nand flash against spurious writing). the status of the port pins during reset is detailed in table 19 . table 19. pin state under reset condition . external rst input in order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a low level has to be applied on the rst pin. a bad level leads to a wrong initialization of the internal registers like sfrs , program counter? and to unpredictable behavior of the microcontroller. a proper device reset initializes the AT85C51SND3b and vectors the cpu to address 0000h. rst input has a pull-up resistor allowing power-on reset by simply connecting an external capacitor to v ss as shown in figure 13 . a warm reset can be applied either directly on the rst pin or indirectly by an internal reset source such as the watchdog timer. resistor value and input characteristics are discussed in the section ?dc characteristics?, page 241 . rst to cpu core iovdd dcpwr dc-dc on /off vbat pfd to peripherals to pads contro l wdt to sysrst out extrst psta.1 wdtrst psta.2 pfdrst psta.0 lvdd r rst hvdd 1.8v reg port 0 port 1 port 2 port 3 port 4 port 5 nfd7:0 nfwp nfce0 float h h h h h float l h
24 AT85C51SND3bx 7632a?mp3?03/06 figure 13. reset circuitry and power-on reset cold reset 2 conditions are required before enabling a cpu start-up: ?v dd must reach the specified v dd range ? the level on x1 input pin must be outside the specification (v ih , v il ) if one of these 2 conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. an active level applied on the rst pin must be asserted till both of the above conditions are met. a reset is active when the level v il is reached and when the pulse width covers the period of time where v dd and the oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset pulse width: ?v dd rise time, ? oscillator startup time. to determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. warm reset to achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running. the number of clock periods is mode independent (x2 or x1). watchdog timer reset as detailed in section ?watchdog timer?, page 75 , the wdt generates a 96-clock period pulse on the rst pin. in order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 k resis - tor must be added as shown in figure 14 . figure 14. reset circuitry for wdt reset-out usage power fail detector the power fail detector (pfd) ensures that whole product is in reset when internal volt - age is out of its limits specification. pfd limits are detailed in the section ?dc characteristics?, page 241 . rst r rst iovdd n iovss to cpu core and peripherals rst iovss + power-on reset rst input circuitry from internal reset source r rst rst iovdd to cpu core and peripherals iovss + n iovss from wdt reset source 1k to other on-board circuitry
25 AT85C51SND3bx 7632a?mp3?03/06 registers reset value = 00011 0000b table 20. pcon register pcon ( 0.87h ) ? power control register 7 6 5 4 3 2 1 0 vbcen vbpen dcpbst gf0 dcen pmlck pd idl bit number bit mnemonic description 7 vbcen battery monitor clock enable bit set to enable the clock of the battery monitoring. clear to disable the clock of the battery monitoring. 6 vbpen battery monitor power enable bit set to power the battery monitoring. clear to unpower the battery monitoring. 5 dcpbst dc-dc converter power boost bit set to disable dc-dc high power boost mode. clear to enable dc-dc high power boost mode. 4 gf0 general-purpose flag 0 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 3 dcen dc-dc converter enable bit set to start the dc-dc converter or maintain its activity while dcpwr pin is asserted. clear to stop the dc-dc converter and shut off the device if not powered by an external power supply. 2 pmlck power mode lock bit set to lock power-down or idle mode entry by preventing pd or idl bits from being set by software. clear to unlock power-down or idle mode entry. 1 pd power-down mode bit cleared by hardware when an interrupt or reset occurs. set to activate the power-down mode when pmlck is cleared. if idl and pd are both set, pd takes precedence. 0 idl idle mode bit cleared by hardware when an interrupt or reset occurs. set to activate the idle mode when pmlck is cleared. if idl and pd are both set, pd takes precedence. table 21. psta register psta (0.86h) ? power status register 7 6 5 4 3 2 1 0 uvdet hvdet - - - wdtrst extrst pfdrst bit number bit mnemonic description 7 uvdet usb voltage detect flag set by hardware when 5v is detected on uvdd pin. cleared by hardware when 5v is not detected on uvdd pin.
26 AT85C51SND3bx 7632a?mp3?03/06 reset value = xx00 0xxxb (1) note: 1. reset value depends on the power supply presence and on the internal reset source. reset value = 0000 0000b 6 hvdet high voltage detect flag set by hardware when 3v is detected on hvdd pin. cleared by hardware when 3v is not detected on hvdd pin. 5-3 - reserved the value of these bits is always 0. do not set these bits. 2 wdtrst watchdog timer reset flag set by hardware when the watchdog timer has overflowed triggering and internal reset. must be cleared by software at power-up. 1 extrst external reset flag set by hardware when the external rst pin is asserted (warm reset). must be cleared by software at power-up. 0 pfdrst power failure detector reset flag set by hardware when the power voltage has been triggered outside its specified value (cold reset). must be cleared by software at power-up. table 22. vbat register vbat (0.85h) ? battery voltage monitor register 7 6 5 4 3 2 1 0 vben vberr - vb4 vb3 vb2 vb1 vb0 bit number bit mnemonic description 7 vben battery monitor enable bit set to enable the battery monitoring. cleared by hardware at the end of conversion 6 vberr battery monitor error flag set by hardware when conversion is out of min/max values. 5 - reserved the value read from this bit is always 0. do not set this bit. 4-0 vb4:0 battery value refer to table 18 for voltage value correspondence. bit number bit mnemonic description
27 AT85C51SND3bx 7632a?mp3?03/06 clock controller the AT85C51SND3bx clock controller is based on an on-chip oscillator feeding two on- chip phase lock loop (pll) dedicated for the usb controller (see section ?usb con - troller?, page 85 ) and the audio controller (see section ?audio controller?, page 149 ). all internal clocks to the peripherals and cpu core are generated by this controller. oscillator x1 and x2 pins of AT85C51SND3bx are the input and the output of a frequency power- optimized single-stage on-chip inverter (see figure 15 ) that can be configured with off- chip components such as a pierce oscillator (see figure 16 ). value of capacitors and crystal characteristics are detailed in the section ?dc characteristics?, page 241 . authorized frequency in order to be able to be able to properly detect the oscillating frequency when in in sys - tem programming mode and then generate the 480mhz requested for usb connection, only the following frequencies are authorized: 12mhz, 13mhz, 16mhz, 19.2mhz, 19.5mhz, 20mhz, 24mhz and 26mhz. power optimization in order to optimize the power consumption, oscillator gain can be adjusted by software depending on the crystal frequency. such optimization is done after reset using oscf1:0 bits in ckcon register (see table 31 ) according to table 23 . moreover if external frequency signal is input (x1 driven by a remote host) it is possible to switch off the internal amplifier by setting the oscamp bit in ckcon register as shown in figure 15 . table 23. oscillator frequency configuration the oscillator outputs a clock: the oscillator clock used to feed the clock generator and the system clock generator. the oscillator cl ock can be disabled by entering the power-down reduction mode as detailed in the section ?power management?, page 18 . figure 15. oscillator block diagram and symbol oscf1:0 crystal clock frequency range (f osc ) 00 22 - 26 mhz (default) 01 18 - 22 mhz 10 14 - 18 mhz. 11 10 - 14 mhz oscf1:0 ckcon4:3 x1 x2 pd pcon.1 osc clock oscillator clock symbol oscillator clock oscamp ckcon.5
28 AT85C51SND3bx 7632a?mp3?03/06 figure 16. crystal connection clock generator the clock generator provides the oscillator and higher frequency clocks to the system, the dfc, the memory controllers: nand flash and mmc controllers, the usb and the high speed serial i/o port. it is based on a 480 mhz pll namely the pll clock followed by a frequency divider giving a broad range of available clock frequency: the clock gen clocks. the clock generation is enabled by setting ckgene bit in cken (see table 32 ). the pll is enabled by setting pllen bit in cken and reports a filtered lock status by the plock flag in cken. as soon as the pll is locked, the generated clocks can be used by the peripherals as detailed in the following sections. figure 17. clock generator block diagram and symbol 480 mhz pll the AT85C51SND3bx pll is based on a phase frequency comparator and lock detector block (pfld) which makes the comparison between the reference clock com - ing from the 4-bit n divider (plln3:0 + 1 in pllclk) and the reverse clock coming from either fixed frequencies or the 4-bit r divider (pllr3:0 + 1 in pllclk) and generates some pulses on the up or down signal depending on the edge position of the reverse clock. these pulses feed the charge pump block (chp) that generates a voltage refer - ence to the 480 mhz voltage controlled osc illator (vco) by injecting or extracting charges from an internal filter. the reverse clock selection mechanism is implemented in order to support many oscillator frequencies and to minimize the pll output jitter. apvss x1 x2 q c1 c2 clock ckgene cken.7 480 mhz pll osc clock plock cken.4 pllen cken.6 clock gen clock generator symbol generator divider 60 mhz 48 mhz 40 mhz 30 mhz 24 mhz 20 mhz 16 mhz pll clock osc 120 mhz
29 AT85C51SND3bx 7632a?mp3?03/06 figure 18. pll block diagram and symbol table 24. pll reverse clock selection pll programming the pll is programmed depending on the oscillator clock frequency. in order to mini - mize the output jitter, f rev must be as higher as possible. table 26 shows the pll programming values and reverse frequency depending on some oscillator frequency. table 25. pll programming values versus input frequency system clock generator in order to increase the system computation throughput, it is possible to switch the sys - tem clock to higher value when pll is enabled. system clock generator block diagram is shown in figure 19 and is based on a frequency selector controlled by syscks1:0 bits in cksel (see table 34 ) according to table 26 . the cpu clock can be disabled by entering the idle reduction mode as detailed in the section ?power management?, page 18 . note: in order to prevent any incorrect operation while dynamically switching the system fre - quency, user must be aware that all peripherals using the peripheral clock as time reference (timers, etc?) will have their time reference modified by this frequency change. pllcks1:0 clock selection (f rev ) 00 12 mhz (default) 01 16 mhz 10 20 mhz 11 12 mhz (pllr + 1) pllcks1:0 cksel.4:3 plln3:0 pllclk.3:0 pll clock symbol up down chp n divider vco pll clock 480 mhz 00 01 10 11 pllr3:0 pllclk.7:4 r divider primary divider 12 mhz 16 mhz 20 mhz pfld f rev f osc (mhz) pllcks1:0 plln3:0 / n pllr3:0 / r f rev (mhz) 12 00 0000 xxxx 12 13 11 1100 / 13 1011 / 12 1 16 01 0000 xxxx 16 19.2 11 0111 / 8 0100 / 5 2.4 19.5 11 1100 / 13 0111 / 8 1.5 20 10 0000 xxxx 20 24 00 0001 / 2 xxxx 12 26 11 1100 / 13 0101 / 6 2
30 AT85C51SND3bx 7632a?mp3?03/06 figure 19. system clock generator block diagram and symbols table 26. system clock selection x2 feature unlike standard c51 products that require 12 clock periods per machine cycle, the AT85C51SND3bx need only 6 clock periods per machine cycle. this feature called the ?x2 feature? can be enabled using the x2 bit (1) in ckcon and allows the AT85C51SND3bx to operate in 6 or 12 clock periods per machine cycle. as shown in figure 19 , both cpu and peripheral clocks are affected by this feature. figure 20 shows the x2 mode switching waveforms. after reset the standard mode is activated. in stan - dard mode the cpu and peripheral clock frequency is the oscillator frequency divided by 2 while in x2 mode, it is the oscillator frequency. figure 20. mode switching waveforms dfc/nfc clock generator in order to optimize the data transfer throughput between the dfc and the nfc, both peripherals share the same clock frequency. the dfc and nfc clock generator block diagram is shown in figure 21 and is based on a frequency selector. frequency selection is done using dnfcks2:0 bits in cksel (see table 33 ) according to table 27 . frequency is enabled by setting dnfcken bit in cken. syscks1:0 clock selection (f sys ) 00 f osc (default) 01 24 mhz 10 30 mhz 11 40 mhz idl pcon.0 x2 ckcon.0 syscks1:0 cksel.1:0 clock gen 24 mhz 30 mhz 40 mhz f sys 00 01 10 11 osc clock peripheral cpu core 0 1 2 clock clock per clock peripheral clock symbol cpu clock cpu core clock symbol aud clock audio clock symbol audio controlle r clock f sys 2 f sys clock x2 bit x2 mode std mode std mode
31 AT85C51SND3bx 7632a?mp3?03/06 figure 21. dfc/nfc clock generator block diagram and symbol table 27. dfc/nfc clock selection mmc clock generator the mmc clock generator block diagram is shown in figure 22 and is based on a fre - quency selector followed by a frequency divider. frequency selection is done using mmccks2:0 bits in mmcclk (see table 35 ) according to table 28 (1) . frequency division is done using mmcdiv4:0 bits in mmcclk according to table 29 . frequency configuration (selection and division) must be done prior to enable the mmc clock generation by setting mmcken bit in cken. note: 1. to allow low frequency as low as 400 khz (frequency needed in mmc identification phase), f osc selection can be divided by 2. figure 22. mmc clock generator block diagram and symbol dnfcks2:0 clock selection (f s ) 000 f osc (default) 001 60 mhz 010 48 mhz 011 40 mhz 100 30 mhz 101 24 mhz 110 20 mhz 111 16 mhz dnfcks2:0 cksel.7:5 clock gen 000 001 010 011 100 101 110 111 60 mhz 48 mhz 40 mhz 30 mhz 24 mhz 20 mhz 16 mhz dnfc clock dfc/nfc clock symbol dnfcken cken.0 f s dfc clock osc nfc clock mmcken cken.3 mmccks2:0 mmcclk.7:5 000 001 010 011 100 101 110 111 60 mhz 48 mhz 30 mhz 24 mhz 20 mhz 16 mhz mmc clock mmc clock symbol clock divider mmcdiv4:0 mmcclk.4:0 f s mmc clock clock gen osc 2 osc
32 AT85C51SND3bx 7632a?mp3?03/06 table 28. mmc clock selection table 29. mmc clock divider sio clock generator as detailed in figure 23 , the sio clock which feeds the internal sio baud rate generator can be programmed using siocks bit in cksel register according to table 30 to gen - erate either the oscillator frequency or a very high frequency allowing very high baud rate when pll is enabled. sio clock is enabled by siocken bit in cken register. figure 23. sio clock generator block diagram and symbol table 30. sio clock selection mmccks2:0 clock selection (f s ) 000 f osc (default) 001 60 mhz 010 48 mhz 011 30 mhz 100 24 mhz 101 20 mhz 110 16 mhz 111 f osc 2 mmcdiv4:0 clock division 00000 disabled (no clock out) 00001 f mmc = f s mmcdiv siocks clock selection (f s ) 0 f osc 1 120 mhz clock gen 120 mhz sio clock sio clock symbol siocken cken.1 sio clock osc 0 1 siocks cksel.2 f s
33 AT85C51SND3bx 7632a?mp3?03/06 registers reset value = 0000 0000b table 31. ckcon register ckcon (0.8fh) ? clock control register 7 6 5 4 3 2 1 0 - wdx2 oscamp oscf1 oscf0 t1x2 t0x2 x2 bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6 wdx2 watchdog clock control bit set to select the oscillator clock divided by 2 as watchdog clock input (x2 independent). clear to select the peripheral clock as watchdog clock input (x2 dependent). 5 oscamp oscillator amplifier control bit set to optimize power consumption by disabling the oscillator amplifier when an external clock is used. clear to enable the oscillator amplifier in case of crystal usage (default). 4-3 oscf1:0 oscillator frequency range bits set this bits according to table 23 to optimize power consumption. 2 t1x2 timer 1 clock control bit set to select the oscillator clock divided by 2 as timer 1 clock input (x2 independent). clear to select the peripheral clock as timer 1 clock input (x2 dependent). 1 t0x2 timer 0 clock control bit set to select the oscillator clock divided by 2 as timer 0 clock input (x2 independent). clear to select the peripheral clock as timer 0 clock input (x2 dependent). 0 x2 system clock control bit clear to select 12 clock periods per machine cycle (std mode, f cpu = f per = f osc / 2). set to select 6 clock periods per machine cycle (x2 mode, f cpu = f per = f osc ).
34 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 32. cken register cken (0. b9h ) ? clock enable register 7 6 5 4 3 2 1 0 ckgene pllen - plock mmcken - siocken dnfcken bit number bit mnemonic description 7 ckgene clock generator enable bit set to enable the clock generator. clear to disable the clock generators. 6 pllen pll enable bit set to enable the 480 mhz pll. clear to disable the 480 mhz pll. 5 - reserved the value read from this bit is always 0. do not set this bit. 4 plock pll lock flag set by hardware when the pll is locked. cleared by hardware when the pll is not locked. 3 mmcken mmc controller clock enable bit set to enable the mmc controller clock. clear to disable the mmc controller clock. 2 - reserved the value read from this bit is always 0. do not set this bit. 1 siocken sio controller clock enable bit set to enable the sio clock. clear to disable the sio clock. 0 dnfcken df controller / nf controller clock enable bit set to enable the dfc/nfc clock. clear to disable the dfc/nfc clock.
35 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b table 33. cksel register cksel (0. bah ) ? clock selection register 7 6 5 4 3 2 1 0 dnfcks2 dnfcks1 dfccks0 pllcks1 pllcks0 siocks syscks1 syscks0 bit number bit mnemonic description 7-5 dnfcks2:0 dfc/nfc clock select bits refer to table 27 for information on selected clock value. 4-3 pllcks1:0 pll reverse clock select bits refer to table 24 for information on selected clock value. 2 siocks sio clock select bit refer to table 30 for information on divided clock value. 1-0 syscks1:0 system clock select bits refer to table 26 for information on divided clock value. table 34. pllclk register pllclk (0. bch ) ? pll clock control register 7 6 5 4 3 2 1 0 pllr3 pllr2 pllr1 pllr0 plln3 plln2 plln1 plln0 bit number bit mnemonic description 7-4 pllr3:0 pll r divider bits 4-bit r divider, r from 1 (pllr3:0 = 0000) to 16 (pllr3:0 = 1111). 3-0 plln3:0 pll n divider bits 4-bit n divider, n from 1 (plln3:0 = 0000) to 16 (plln3:0 = 1111). table 35. mmcclk register mmcclk (0. bdh ) ? mmc clock control register 7 6 5 4 3 2 1 0 mmccks2 mmccks1 mmccks0 mmcdiv4 mmcdiv3 mmcdiv2 mmcdiv1 mmcdiv0 bit number bit mnemonic description 7-5 mmccks2:0 mmc clock select bits refer to table 28 for information on selected clock value. 4-0 mmcdiv4:0 mmc clock divider bits refer to table 29 for information on divided clock value.
36 AT85C51SND3bx 7632a?mp3?03/06 special function registers sfr pagination the AT85C51SND3bx implement a sfr pagination mechanism which allows mapping of high number of peripherals in the sfr space. as shown in figure 24 , four pages are accessible through the ppcon (peripheral pagination control) register (see table 37 ). the four bits of ppcon: pps0 to pps3 are used to select one page as detailed in table 36 . setting one bit of ppcon using the setb instruction automatically clears the 7 oth - ers: e.g. if page 0 is selected, selecting page 3 is done by the instruction setb pps3 which clears pps0. by default, after reset selected page is page 0. the ppcon content is automatically saved in a specific stack at each interrupt service routine entry during vectorization and restored at exit during reti execution. figure 24. sfr pagination block diagram table 36. page selection truth table reset value = 0000 0001b pps3 pps2 pps1 pps0 selected page 0 0 0 0 page 0 x x x 1 page 0 x x 1 0 page 1 x 1 0 0 page 2 1 0 0 0 page 3 table 37. ppcon register ppcon (y.c0h) ? peripheral page control register 7 6 5 4 3 2 1 0 - - - - pps3 pps2 pps1 pps0 bit number bit mnemonic description 7-4 - reserved the value read from these bits is always 0. do not set these bits. 3-0 pps3:0 peripheral page select bits refer to table 36 for page decoding information. 0 1 sfr decoder 2 pps0 ppcon.0 pps1 ppcon.1 4 to 2 encoder 2 3 pps2 ppcon.2 pps3 ppcon.3
37 AT85C51SND3bx 7632a?mp3?03/06 sfr registers the special function registers ( sfrs ) of the AT85C51SND3bx fall into the categories detailed in table 39 to table 58 . address is identified as ?p.xxh? where p can take the values detailed in table 38 and xxh is the hexadecimal address from 80h to ffh table 38. page address notation the sfrs mapping within pages is provided together with sfr reset value in table 58 to table 58 . in these tables, the bit-addressable registers are identified by note 1. note: available in AT85C51SND3b3 only. p comment y register mapped in all pages 3-0 register mapped in the corresponding page table 39. c51 core sfrs mnemonic add name 7 6 5 4 3 2 1 0 acc y. e 0 h accumulator b y. f 0 h b register psw y. d 0 h program status word cy ac f0 rs1 rs0 ov f1 p sp y.81h stack pointer dpl y.82h data pointer low byte dph y.83h data pointer high byte ppcon y. c 0 h peripheral pagination - - - - pps3:0 table 40. power and system management mnemonic add name 7 6 5 4 3 2 1 0 pcon 0.87h power control vbcen vbpen dcpbst gf0 dcen* pmlck pd idl psta 0.86h power status uvdet hvdet - - - wdtrst extrst pfdrst auxr1 0.a2h auxiliary register 1 - - - - gf3 0 - dps vbat 0.85h battery voltage monitoring vben vberr - vb4:0 svers 3.97h silicon version sv7:0 table 41. clock management unit sfrs mnemonic add name 7 6 5 4 3 2 1 0 ckcon 0.8fh clock control - wdx2 - oscf1:0 t1x2 t0x2 x2 cken 0.b9h clock enable ckgene pllen - plock mmcken - siocken dfcken cksel 0.bah clock selection dnfcks2:0 pllcks1:0 siocks syscks1:0 pllclk 0.bch pll clock pllr3:0 plln3:0 mmcclk 0.bdh mmc clock mmccks2:0 mmcdiv4:0
38 AT85C51SND3bx 7632a?mp3?03/06 table 42. interrupt sfrs mnemonic add name 7 6 5 4 3 2 1 0 ien0 0.a8h interrupt enable control 0 ea eaup edfc es et1 ex1 et0 ex0 ien1 0.b1h interrupt enable control 1 - - emmc enfc espi epsi ekb eusb iph0 0.b7h interrupt priority control high 0 - iphaup iphdfc iphs ipht1 iphx1 ipht0 iphx0 ipl0 0.b8h interrupt priority control low 0 - iplaup ipldfc ipls iplt1 iplx1 iplt0 iplx0 iph1 0.b3h interrupt priority control high 1 - - iphmmc iphnfc iphspi iphpsi iphkb iphusb ipl1 0.b2h interrupt priority control low 1 - - iplmmc iplnfc iplspi iplpsi iplkb iplusb table 43. i/o port sfrs mnemonic add name 7 6 5 4 3 2 1 0 p0 y.80h 8-bit port 0 p1 y.90h 8-bit port 1 p2 y. a 0 h 8-bit port 2 p3 y. b 0 h 8-bit port 3 p4 0.98h 8-bit port 4 p5 0.c8h 4-bit port 5 table 44. timer sfrs mnemonic add name 7 6 5 4 3 2 1 0 tcon 0.88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 0.89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 tl0 0.8ah timer/counter 0 low byte th0 0.8ch timer/counter 0 high byte tl1 0.8bh timer/counter 1 low byte th1 0.8dh timer/counter 1 high byte wdtrst 0.a6h watchdog timer reset wdtprg 0.a7h watchdog timer program - - - - - wto2:0 table 45. ram interface mnemonic add name 7 6 5 4 3 2 1 0 rdfcal 1.fdh ram dfc low address byte ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 rdfcam 1.feh ram dfc medium address byte ra15 ra14 ra13 ra12 ra11 ra10 ra9 ra8 rdfcah 1.ffh ram dfc higher address byte - - - - - - - ra16
39 AT85C51SND3bx 7632a?mp3?03/06 table 46. memory management sfrs mnemonic add name 7 6 5 4 3 2 1 0 memcbax 0.f2h memory code base address cbax16:9 memdbax 0.f3h memory data base address dbax16:9 memxbax 0.f4h memory xdata base address xbax16:9 memcsx 0.f5h memory code size csx7:0 memxsx 0.f6h memory xdata size xsx7:0 table 47. scheduler sfrs mnemonic add name 7 6 5 4 3 2 1 0 schclk 0.feh scheduler clocks - schidl2:0 - - - - schgpr3 y. f 9 h 32-bit general purpose register gpr31:24 schgpr2 y. fa h 32-bit general purpose register gpr23:16 schgpr1 y. f b h 32-bit general purpose register gpr15:8 schgpr0 y. f c h 32-bit general purpose register gpr7:0 table 48. data flow controller sfrs mnemonic add name 7 6 5 4 3 2 1 0 dfcon 1.89h dfc control dfres - dfcrcen dfprio1:0 dfabtm dfen dfcsta 1.88h dfc channel status drdy1 srdy1 eofi1 dfbsy1 drdy0 srdy0 eofi0 dfbsy0 dfccon 1.85h dfc channel control dfabt1 eofe1 eofia1 - dfabt0 eofe0 eofia0 - dfd0 1.8ah dfc channel 0 descriptor dfd0d7:0 dfd1 1.8bh dfc channel 1 descriptor dfd1d7:0 dfcrc 1.8ch dfc crc16 data crcd7:0 table 49. usb controller sfrs mnemonic add name 7 6 5 4 3 2 1 0 usb general registers usbcon 1.e1h usb general control usbe host frzclk otgpade - - idte vbuste usbsta 1.e2h usb general status - - - - - speed id vbus usbint 1.e3h usb general interrupt - - - - - - idti vbusti udpaddh 1.e4h usb dpram direct access high dpacc - - - - dpadd10:8 udpaddl 1.e5h usb dpram direct access low dpadd7:0 otgcon 1.e6h usb otg control - - hnpreq srpreq srpsel vbushwc vbusreq vbusrqc otgien 1.e7h usb otg interrupt enable - - stoe hnperre roleexe bcerre vberre srpe otgint 1.d1h usb otg interrupt - - stoi hnperri roleexi bcerri vberri srpi
40 AT85C51SND3bx 7632a?mp3?03/06 usb device registers (host cleared) udcon 1.d9h device global control - - - - - - rmwkup detach udint 1.d8h device global interrupt (bit addressable) - uprsmi eorsmi wakeupi eorsti sofi msofi suspi udien 1.dah device global interrupt enable - uprsme eorsme wakeupe eorste sofe msofe suspe udaddr 1.dbh device address adden uadd6:0 udfnumh 1.dch device frame number high - - - - - fnum10:8 udfnuml 1.ddh device frame number low fnum7:0 udmfn 1.deh device micro frame number - - - fncerr - mfnum2:0 udtst 1.dfh device test - - opmode2 tstpckt tstk tstj spdconf usb host registers (host set) uhcon 1.d9h usb host general control - - - - - resume reset sofe uhint 1.d8h usb host general interrupt (bit addressable) - hwupi hsofi rxrsmi rsmedi rsti ddisci dconni uhien 1.dah usb host general interrupt en - hwupe hsofe rxrsme rsmede rste ddisce dconne uhaddr 1.dbh usb host address - haddr6:0 uhfnumh 1.dch usb host frame number high - - - - - fnum10:8 uhfnuml 1.ddh usb host frame number low fnum7:0 uhflen 1.deh usb host frame length flen7:0 usb device endpoint registers (host cleared) uenum 1.c9h endpoint number selection - - - - - epnum2:0 uerst 1.cah endpoint reset - eprst6:0 ueconx 1.cbh endpoint control - - stallrq stallrqc rstdt epnums dfcrdy epen uecfg0x 1.cch endpoint configuration 1 eptype1:0 - - isosw autosw nyetdis epdir uecfg1x 1.cdh endpoint configuration 0 - epsize2:0 epbk1:0 alloc - uesta0x 1.ceh endpoint status 0 cfgok overfi underfi zlpseen dtseq1:0 nbusybk1:0 uesta1x 1.cfh endpoint status 1 - - - - - ctrldir currbk1:0 ueintx 1.c8h endpoint interrupt (bit addressable) fifocon nakini rwal nakouti rxstpi rxouti stalli txini ueienx 1.d2h endpoint interrupt enable flerre nakine - nakoute rxstpe rxoute stalle txine uedatx 1.d3h endpoint data dat7:0 uebchx 1.d4h endpoint byte counter high - - - - - byct10:8 uebclx 1.d5h endpoint byte counter low byct7:0 ueint 1.d6h endpoint interrupt - epint6:0 table 49. usb controller sfrs mnemonicaddname 76543210
41 AT85C51SND3bx 7632a?mp3?03/06 usb pipe registers (host set) upnum 1.c9h usb host pipe number - - - - - pnum2:0 uprst 1.cah usb host pipe reset - prst6:0 upconx 1.cbh usb pipe control - pfreeze inmode autosw rstdt pnums dfcrdy pen upcfg0x 1.cch usb pipe configuration 0 ptype1:0 ptoken1:0 pepnum3:0 upcfg1x 1.cdh usb pipe configuration 1 - psize2:0 pbk1:0 alloc - upcfg2x 1.cfh usb pipe configuration 2 intfrq7:0 upstax 1.ceh usb pipe status cfgok overfi underfi - dtseq1:0 nbusybk1:0 upinrqx 1.dfh usb pipe in request inrq7:0 uperrx 1.d7h usb pipe error - counter1:0 crc16 timeout pid datapid datatgl upintx 1.c8h usb pipe interrupt (bit addressable) fifocon nakedi rwal perri txstpi txouti rxstalli rxini upienx 1.d2h usb pipe interrupt enable flerre nakede - perre txstpe txoute rxstalle rxine updatx 1.d3h usb pipe data pdat7:0 upbchx 1.d4h usb pipe byte counter (high) - - - - - pbyct10:8 upbclx 1.d5h usb pipe byte counter (low) pbyct7:0 upint 1.d6h usb pipe general interrupt pint7:0 table 49. usb controller sfrs mnemonicaddname 76543210 table 50. nfc sfrs mnemonic add name 7 6 5 4 3 2 1 0 nfcfg 1.99h nf configuration (fifo 8 b) cfg7:0 nflog 1.9ah nf logical value (2 b) log7:0 nfcon 1.9bh nf control - - trs reset wp spzen eccen en nferr 1.9ch nf error information (fifo 4 b) err7:0 nfadr 1.9dh nf row address adr7:0 nfadc 1.9eh nf column address adc7:0 nfcmd 1.9fh nf command cmd7:0 nfact 1.a1h nf action - - - ext1:0 act2:0 nfdat 1.a2h nf data dat7:0 nfdatf 1.a3h nf data and fetch next datf7:0 nfsta 1.98h nf controller status smcd smlck - eop necc2:0 run nfecc 1.a4h nf ecc 1 and 2 (fifo 6 b) ecc7:0 nfint 1.a5h nf interrupt - - - smcti ilgli eccrdyi eccerri stopi nfien 1.a6h nf interrupt enable - - - smcte ilgle eccrdye eccerre stope nfudat 1.a7h nf user data udata7:0
42 AT85C51SND3bx 7632a?mp3?03/06 nfbph 1.94h nf byte position (msb) bp15:8 nfbpl 1.95h nf byte position (lsb) bp7:0 table 50. nfc sfrs mnemonicaddname 76543210 table 51. mmc controller sfrs mnemonic add name 7 6 5 4 3 2 1 0 mmcon0 1.b1h mmc control 0 - dptrr crptr ctptr mblock dfmt rfmt crcdis mmcon1 1.b2h mmc control 1 blen11:8 datdir daten rxcen txcen mmcon2 1.b3h mmc control 2 fck dcr ccr dbsize1:0 datd1:0 mmcen mmblp 1.b4h mmc block length blen7:0 mmsta 1.b5h mmc status sdwp cdet cbusy crc16s datfs crc7s wfrs hfrs mmdat 1.b6h mmc data md7:0 mmcmd 1.b7h mmc command mc7:0 mmint 1.beh mmc interrupt cdeti eori eoci eofi wfri hfri eobi - mmmsk 1.bfh mmc interrupt mask cdetm eorm eocm eofm wfrm hfrm eobm - table 52. audio controller sfrs mnemonic add name 7 6 5 4 3 2 1 0 aucon 1.f1h audio controller control bpen vsurnd bboost mixen equdis - - accken apcon0 1.f2h audio processor control 0 0 apcmd6:0 apcon1 1.f3h audio processor control 1 - - abacc abwpr abrpr absplit apload dapen apsta 1.eah audio processor status apstat7:0 apdat 1.ebh audio processor data apdat7:0 apint 1.f4h audio processor interrupt apgpi3 apgpi2 apgpi1 apgpi0 apevti aclipi aprdyi apreqi apien 1.e9h audio processor interrupt enable apgpe3 apgpe2 apgpe1 apgpe0 apevte aclipe aprdye apreqe aptim0 2.c6h audio processor timer 0 apt7:0 aptim1 2.c7h audio processor timer 1 apt15:8 aptim2 2.c9h audio processor timer 2 apt23:16 aprdvol 2.f1h audio processor right channel digital volume - - - dvr4:0 apldvol 2.f2h audio processor left channel digital volume - - - dvl4:0 apbdvol 2.f3h audio processor bass band digital volume - - - dvb4:0 apmdvol 2.f4h audio processor medium band digital volume - - - dvm4:0 aptdvol 2.f5h audio processor treble band digital volume - - - dvt4:0
43 AT85C51SND3bx 7632a?mp3?03/06 note: available in AT85C51SND3b2 & AT85C51SND3b3 only. apebs 2.f6h audio processor equalizer band select - - - - 0 eqbs2:0 apelev 2.f7h audio processor equalizer level - - - eqlev4:0 accon 2.eah audio codec control - ambsel amben aissel aien aodrv* aossel* aoen* acaux 2.e4h audio codec auxiliary - - - - - - aodis* aopre* acorg* 2.ebh audio codec right output gain - - - aorg4:0* acolg* 2.ech audio codec left output gain - - - aolg4:0* acipg 2.edh audio codec input preamp gain - - - - ailpg aipg2:0 adicon0 2.eeh audio dac interface control 0 - - - cspol dsize overs1:0 adien adicon1 2.efh audio dac interface control 1 - - - just4:0 table 53. audio stream codec sfrs mnemonicaddname 76543210 ascon 2.e1h audio stream control depends on the audio codec firmware assta0 2.e2h audio stream status 0 assta1 2.e3h audio stream status 1 assta2 2.e9h audio stream status 2 table 52. audio controller sfrs mnemonicaddname 76543210 table 54. psi controller sfrs mnemonic add name 7 6 5 4 3 2 1 0 psisth 1.ach psi status host pshbsy pssth6:0 psicon 1.adh psi control psen psbsye psrune psws2:0 - - psista 1.aeh psi status psempty psbsy psrun psrdy - - - - psidat 1.afh psi data psd7:0 table 55. spi controller sfrs mnemonic add name 7 6 5 4 3 2 1 0 spcon 1.91h spi control spr2 spen ssdis mstr cpol cpha spr1 spr0 spscr 1.92h spi status and control spif - ovr modf spte uartm spteie modfie spdat 1.93h spi data spd7:0 table 56. serial i/o port sfrs mnemonic add name 7 6 5 4 3 2 1 0 scon 0.91h sio control sioen pmod1:0 pben stop dlen gbit1:0 sfcon 0.95h sio flow control ovsf3:0 ctsen rtsen rtsth1:0
44 AT85C51SND3bx 7632a?mp3?03/06 sint 1.a8h sio interrupt - - eoti oei pei fei ti ri sien 1.a9h sio interrupt enable - - eotie oeie peie feie tie rie sbuf 1.aah sio data buffer siod7:0 sbrg0 0.92h sio baud rate generator 0 cdiv7:0 sbrg1 0.93h sio baud rate generator 1 bdiv7:0 sbrg2 0.94h sio baud rate generator 2 adiv7:0 table 56. serial i/o port sfrs mnemonicaddname 76543210 table 57. lcd interface sfrs mnemonic add name 7 6 5 4 3 2 1 0 lcdcon0 1.96h lcd control 0 buinv lcifs adsuh1 adsuh0 accw3 accw2 accw1 accw0 lcdcon1 1.8eh lcd control 1 slw1:0 rscmd lcycw lcyct lcen lcrd lcrs lcdsta 1.8fh lcd status - - - - - - - lcbusy lcddat 1.97h lcd data ld7:0 lcdbum 1.8dh lcd busy mask bum7:0 table 58. keyboard interface sfrs mnemonic add name 7 6 5 4 3 2 1 0 kbcon 0.a3h keyboard control kinl3:0 kinm3:0 kbsta 0.a4h keyboard status kpde kdcpe kdcpl - kinf3:0
45 AT85C51SND3bx 7632a?mp3?03/06 notes: 1. sfr registers with least significant nibble address equal to 0 or 8 are bit-addressable. table 59. sfr page 0: addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h schgpr3 0000 0000 schgpr2 0000 0000 schgpr1 0000 0000 schgpr0 0000 0000 schclk 0000 0000 ffh f0h b (1) 0000 0000 memcon 0000 0001 memcbax 0 0000 000 memdbax 0 1111 111 memxbax 0 1111 000 memcsx 1110 1111 memxsx 0000 1110 f7h e8h efh e0h acc (1) 0000 0000 e7h d8h dfh d0h psw (1) 0000 0000 d7h c8h p5 (1) 1111 1111 cfh c0h ppcon (1) 0000 0001 c7h b8h ipl0 (1) x000 0000 cken 0000 0000 dfcclk 0000 0000 nfcclk 0000 0000 mmcclk 0000 0000 bfh b0h p3 (1) 1111 1111 ien1 0000 0000 ipl1 0000 0000 iph1 0000 0000 iph0 x000 0000 b7h a8h ien0 (1) 0000 0000 afh a0h p2 (1) 1111 1111 auxr1 xxxx 00x0 kbcon 0000 1111 kbsta 0010 0000 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h p4 (1) 1111 1111 9fh 90h p1 (1) 1111 1111 scon 0000 0000 sbrg0 0000 0000 sbrg1 0000 0000 sbrg2 0000 0000 sfcon 0000 0000 97h 88h tcon (1) 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckcon 0000 0000 8fh 80h p0 (1) 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 vbat 0000 0000 psta xx00 0xxx pcon 0011 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
46 AT85C51SND3bx 7632a?mp3?03/06 note: 1. sfr registers with least significant nibble address equal to 0 or 8 are bit-addressable. table 60. sfr page 1: addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h schgpr3 0000 0000 schgpr2 0000 0000 schgpr1 0000 0000 schgpr0 0000 0000 rdfcal 0000 0000 rdfcam 0000 0000 rdfcah 0000 0000 ffh f0h b (1) 0000 0000 aucon 0000 0000 apcon0 0000 0000 apcon1 0000 0000 apint 0000 0000 f7h e8h apien 0000 0000 apsta 0000 0000 apdat 0000 0000 efh e0h acc (1) 0000 0000 usbcon 0010 0000 usbsta 0000 00xx usbint 0000 000x udpaddh 0000 0000 udpaddl 0000 0000 otgcon 0000 0000 otgien 0000 0000 e7h d8h udint (1) 0000 0000 uhint (1) 0000 0000 udcon 0000 0001 uhcon 0000 0000 udien 0000 0000 uhien 0000 0000 udaddr 0000 0000 uhaddr 0000 0000 udfnumh 0000 0000 uhfnumh 0000 0000 udfnuml 0000 0000 uhfnuml 0000 0000 udmfn 0000 0000 uhflen 0000 0000 udtst 0000 0000 upinrqx 0000 0000 dfh d0h psw (1) 0000 0000 otgint 0000 0000 ueienx 0000 0000 upienx 0000 0000 uedatx 0000 0000 updatx 0000 0000 uebchx 0000 0000 upbchx 0000 0000 uebclx 0000 0000 upbclx 0000 0000 ueint 0000 0000 upint 0000 0000 uperrx 0000 0000 d7h c8h ueintx (1) 0000 0000 upintx (1) 0000 0000 uenum 0000 0000 upnum 0000 0000 uerst 0000 0000 uprst 0000 0000 ueconx 0000 0000 upconx 0000 0000 uecfg0x 0000 0000 upcfg0x 0000 0000 uecfg1x 0000 0000 upcfg1x 0000 0000 uesta0x 0000 0000 upstax 0000 0100 uesta1x 0000 0000 upcfg2x 0000 0000 cfh c0h ppcon (1) 0000 0001 c7h b8h mmint 0000 0000 mmmsk 1111 1110 bfh b0h p3 (1) 1111 1111 mmcon0 0000 0010 mmcon1 0000 0000 mmcon2 0000 0000 mmblp 0000 0000 mmsta xx00 0000 mmdat 1111 1111 mmcmd 1111 1111 b7h a8h sint (1) 0x10 0010 sien 0000 0000 sbuf xxxx xxxx psith 0000 0000 psicon 0000 0000 psista 1000 0000 psidat 0000 0000 afh a0h p2 (1) 1111 1111 nfact 0000 0000 nfdat 0000 0000 nfdatf 0000 0000 nfecc 0000 0000 nfint 0000 0000 nfien 0000 0000 nfudat xxxx xxxx a7h 98h nfsta (1) 0000 0000 nfcfg 0000 0000 nflog 0000 0000 nfcon 0000 0000 nferr 0000 0000 nfadr 0000 0000 nfadc 0000 0000 nfcmd 0000 0000 9fh 90h p1 (1) 1111 1111 spcon 0001 0100 spscr 0000 1000 spdat xxxx xxxx nfbph 0000 0000 nfbpl 0000 0000 lcdcon0 0000 0000 lcddat 0000 0000 97h 88h dfcsta (1) 0000 0000 dfcon 0000 0000 dfd0 0000 0000 dfd1 0000 0000 dfcrc 0000 0000 lcdbum 0000 0000 lcdcon1 0000 0000 lcdsta 0000 0000 8fh 80h p0 (1) 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 dfccon 0000 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
47 AT85C51SND3bx 7632a?mp3?03/06 notes: 1. sfr registers with least significant nibble address equal to 0 or 8 are bit-addressable. 2. available in AT85C51SND3b2 & AT85C51SND3b3 only. table 61. sfr page 2: addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h schgpr3 0000 0000 schgpr2 0000 0000 schgpr1 0000 0000 schgpr0 0000 0000 ffh f0h b (1) 0000 0000 aprdvol 0000 0011 apldvol 0000 0011 apbdvol 0001 1111 apmdvol 0001 1111 aptdvol 0001 1111 f7h e8h assta2 0000 0000 accon 0000 0000 acorg (1) 0000 0000 acolg (1) 0000 0000 acipg 0000 0000 adicon0 0000 0000 adicon1 0000 0000 efh e0h acc (1) 0000 0000 ascon 0000 0000 assta0 0000 0000 assta1 0000 0000 acaux 0000 0000 e7h d8h dfh d0h psw (1) 0000 0000 d7h c8h aptim2 0000 0000 cfh c0h ppcon (1) 0000 0001 aptim0 0000 0000 aptim1 0000 0000 c7h b8h bfh b0h p3 (1) 1111 1111 b7h a8h afh a0h p2 (1) 1111 1111 a7h 98h 9fh 90h p1 (1) 1111 1111 97h 88h 8fh 80h p0 (1) 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
48 AT85C51SND3bx 7632a?mp3?03/06 notes: 1. sfr registers with least significant nibble address equal to 0 or 8 are bit-addressable. 2. svers reset value depends on the silicon version 1111 1011 for AT85C51SND3b pr oduct. table 62. sfr page 3: addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h schgpr3 0000 0000 schgpr2 0000 0000 schgpr1 0000 0000 schgpr0 0000 0000 ffh f0h b (1) 0000 0000 f7h e8h efh e0h acc (1) 0000 0000 e7h d8h dfh d0h psw (1) 0000 0000 d7h c8h cfh c0h ppcon (1) 0000 0001 c7h b8h bfh b0h p3 (1) 1111 1111 b7h a8h afh a0h p2 (1) 1111 1111 a7h 98h 9fh 90h p1 (1) 1111 1111 svers (2) xxxx xxxx 97h 88h 8fh 80h p0 (1) 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
49 AT85C51SND3bx 7632a?mp3?03/06 memory space the AT85C51SND3bx provide an ?all in one? 64k bytes of ram split between the three standard c51 memory segments: ?code ?data ?xdata to satisfy application needs in term of code and xdata sizes, size and base address of xdata and code segments and base address of data segment can be dynami - cally configured. figure 25 shows the memory space organization. figure 25. memory organization memory segments code segment the AT85C51SND3bx execute up to 64k bytes of program/code memory. the AT85C51SND3bx implement an additional 4k bytes of on-chip boot rom memory. this boot memory is delivered programmed with a boot strap software allowing loading of the application code from the nand flash memory to the internal ram. it also con - tains a boot loader software allowing in-system programming (isp). data segment the data segment is mapped in two separate segments: ? the lower 128 bytes ram segment ? the upper 128 bytes ram segment lower 128 bytes the lower 128 bytes of ram (see figure 26 ) are accessible from address 00h to 7fh using direct or indirect addressing modes. the lowest 32 bytes are grouped into 4 banks of 8 registers (r0 to r7). 2 bits rs0 and rs1 in psw register (see table 64 ) select which bank is in use according to table 63 . this allows more efficient use of code space, since register instructions are shorter than instructions that use direct address - ing, and can be used for context switching in interrupt service routines. 8k bytes secured boot rom 11fffh 10000h 0000h 64k bytes ram - ffffh code data xdata memory controller dfc bus cpu bus
50 AT85C51SND3bx 7632a?mp3?03/06 table 63. register bank selection the next 16 bytes above the register banks form a block of bit-addressable memory space. the c51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h to 7fh. figure 26. lower 128 bytes internal ram organization upper 128 bytes the upper 128 bytes of ram are accessible from address 80h to ffh using only indirect addressing mode. using direct addressing mode within this address range selects the special function registers, sfrs . for information on this segment, refer to the section ?special function registers?, page 36 . xdata segment the on-chip expanded ram (xram) are accessible using indirect addressing mode through movx instructions. memory configuration as shown in figure 25 , the 64kb addressing space of the c51 is artificially increased by usage of logical address over a physical one. for example, the boot memory which con - tains the bootstrap software is implemented at physical address 10000h but is starting at logical address code 0000h which means that the bootstrap is first executed when a system reset occurs. to achieve such logical mapping over the physical memory, some registers have been implemented to give the base address of the memory segments and their size: ?memcbax (see table 65 ) for the code segment base address. ?memdbax (see table 66 ) for the data segment base address. ? memxbax (see table 67 ) for the xdata segment base address. ? memcsx (see table 68 ) for the code segment size. ? memxsx (see table 69 ) for the code segment size. the data segment is not programmable in size as it is a fixed 256-byte segment. rs1 rs0 description 0 0 register bank 0 from 00h to 07h 0 1 register bank 1 from 08h to 0fh 1 0 register bank 2 from 10h to 17h 1 1 register bank 3 from 18h to 1fh bit-addressable space 4 banks of 8 registers r0-r7 30h 7fh (bit addresses 0-7fh) 20h 2fh 18h 1fh 10h 17h 08h 0fh 00h 07h
51 AT85C51SND3bx 7632a?mp3?03/06 the figure 27 shows the memory segments configuration after bootstrap execution along with an example of user memory segments configuration done during firmware start-up. in this figure italicized address are the logical address within segments. figure 27. memory segment configuration registers reset value = 0000 0000b 0000h ffffh ff00h feffh f000h efffh 00h ffh 256-byte data 000h effh 3840-byte xdata 60-kbyte code efffh 0000h 0000h ffffh ff00h feffh e000h dfffh 00h ffh 256-byte data 000h 1effh 7936-byte xdata 56-kbyte code dfffh 0000h default configuration user configuration example memcbax = 00h memxbax = 78h memdbax = 7fh memcsx = efh memxsx = 0eh memcbax = 00h memxbax = 70h memdbax = 7fh memcsx = dfh memxsx = 1eh table 64. psw register psw (s:8eh) ? program status word register 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p bit number bit mnemonic description 7 cy carry flag carry out from bit 1 of alu operands. 6 ac auxiliary carry flag carry out from bit 1 of addition operands. 5 f0 user definable flag 0 4-3 rs1:0 register bank select bits refer to table 63 for bits description. 2 ov overflow flag overflow set by arithmetic operations. 1 f1 user definable flag 1 0 p parity bit set when acc contains an odd number of 1?s. cleared when acc contains an even number of 1?s.
52 AT85C51SND3bx 7632a?mp3?03/06 reset value memcba0 = 0 0000 000b reset value memdbax = 0 1111 111b reset value memxbax = 0 1111 000b table 65. memcbax register memcbax (0.f2h) ? memory management code base address register 7 6 5 4 3 2 1 0 cbax16 cbax15 cbax14 cbax13 cbax12 cbax11 cbax10 cbax9 bit number bit mnemonic description 7-0 cbax16:9 code base address most significant bits of context mempid 17-bit code base address: x xxxx xxx0 0000 0000b. 512-byte alignment, no offset. table 66. memdbax register memdbax (0.f3h) ? memory management data base address register 7 6 5 4 3 2 1 0 dbax16 dbax15 dbax14 dbax13 dbax12 dbax11 dbax10 dbax9 bit number bit mnemonic description 7-0 dbax16:9 data base address most significant bits of context mempid 17-bit data base address: x xxxx xxx1 0000 0000b. 512-byte alignment with 256-byte offset. table 67. memxbax register memxbax (0.f4h) ? memory man agement xdata base address registers 7 6 5 4 3 2 1 0 xbax16 xbax15 xbax14 xbax13 xbax12 xbax11 xbax10 xbax9 bit number bit mnemonic description 7-0 xbax16:9 xdata base address most significant bits of context mempid 17-bit code base address: x xxxx xxx0 0000 0000b. 512-byte alignment, no offset. table 68. memcsx register memcsx (0.f5h) ? memory management code size register 7 6 5 4 3 2 1 0 csx7 csx6 csx5 csx4 csx3 csx2 csx1 csx0
53 AT85C51SND3bx 7632a?mp3?03/06 reset value memcsx = 1110 1111b reset value memxsx = 0000 1110b bit number bit mnemonic description 7-0 csx7:0 code size bits of context mempid size is equals to (csx+1) x 256 bytes. code sizes available: from 256 bytes to 64 kbytes, by 256-byte steps. table 69. memxsx register memxsx (0.f6h) ? memory m anagement xdata size register 7 6 5 4 3 2 1 0 xsx7 xsx6 xsx5 xsx4 xsx3 xsx2 xsx1 xsx0 bit number bit mnemonic description 7-0 xsx7:0 xdata size bits of context mempid size is equals to (xsx+1) x 256 bytes. xdata sizes available: from 256 bytes to 64 kbytes, by 256-byte steps.
54 AT85C51SND3bx 7632a?mp3?03/06
55 AT85C51SND3bx 7632a?mp3?03/06 interrupt system the AT85C51SND3bx, like other control-oriented computer architectures, employ a program interrupt method. this operation branches to a subroutine and performs some service in response to the interrupt. when the subroutine completes, execution resumes at the point where the interrupt occurred. interrupts may occur as a result of internal AT85C51SND3bx activity (e.g., timer overflow) or at the initiation of electrical signals external to the microcontroller (e.g., keyboard). in all cases, interrupt operation is pro - grammed by the syst em designer, who determines priority of interrupt service relative to normal code execution and other interrupt service routines. all of the interrupt sources are enabled or disabled by the system designer and may be manipulated dynamically. a typical interrupt event chain occurs as follows: ? an internal or external device initiates an interrupt-request signal. the AT85C51SND3bx, latch this event into a flag buffer. ? the priority of the flag is compared to the priority of other interrupts by the interrupt handler. a high priority causes the handler to set an interrupt flag. ? this signals the instruction execution unit to execute a context switch. this context switch breaks the current flow of instruction sequences. the execution unit completes the current instruction prior to a save of the program counter (pc) and reloads the pc with the start address of a software service routine. ? the software service routine executes assigned tasks and as a final activity performs a reti (return from interrupt) instruction. this instruction signals completion of the interrupt, resets the interrupt-in-progress priority and reloads the program counter. program operation then continues from the original point of interruption. six interrupt registers are used to control the interrupt system: ? two 8-bit registers are used to enable separately the interrupt sources: ien0 and ien1 registers (see table 72 and table 73). ? four 8-bit registers are used to establish the priority level of the different sources: iph0, ipl0, iph1 and ipl1 registers (see table 74 to table 77). interrupt system priorities each interrupt sources of the AT85C51SND3bx can be individually programmed to one of four priority levels. this is accomplished by one bit in the interrupt priority high regis - ters (iph0 and iph1) and one bit in the interrupt priority low registers (ipl0 and ipl1). this provides each interrupt source four possible priority levels according to table 70 . table 70. priority levels a low-priority interrupt is always interrupted by a higher priority interrupt but not by another interrupt of lower or equal priority. higher priority interrupts are serviced before lower priority interrupts. the response to simultaneous occurrence of equal priority inter - rupts is determined by an internal hardware polling sequence detailed in table 71 . thus, within each priority level there is a second priority structure determined by the polling sequence. the interrupt control system is shown in interrupt control system . iphxx iplxx priority level 0 0 0 lowest 0 1 1 1 0 2 1 1 3 highest
56 AT85C51SND3bx 7632a?mp3?03/06 table 71. priority within same level interrupt name priority number interrupt address vectors interrupt request flag cleared by hardware (h) or by software (s) int0 0 (highest priority) c:0003h h if edge, s if level timer 0 1 c:000bh h int1 2 c:0013h h if edge, s if level timer 1 3 c:001bh h serial i/o port 4 c:0023h s data flow controller 5 c:002bh s audio processor 6 c:0033h s usb controller 7 c:003bh s keyboard 8 c:0043h s parallel slave interface 9 c:004bh s serial peripheral interface 10 c:0053h s nand flash controller 11 c:005bh s mmc controller 12 c:0063h s reserved 13 c:006bh - reserved 14 (lowest priority) c:0073h -
57 AT85C51SND3bx 7632a?mp3?03/06 figure 28. interrupt control system epsi ien1.2 ekb ien1.1 emmc ien1.5 espi ien1.3 ex0 ien0.0 00 01 10 11 ea ien0.7 ex1 ien0.2 et0 ien0.1 edfc ien0.5 et1 ien0.3 eaup ien0.6 enfc ien1.4 eusb ien1.0 interrupt enable lowest priority interrupts highest priority enable 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 priority interrupts es ien0.4 00 01 10 11 iph/l 00 01 10 11 external interrupt 0 external interrupt 1 timer 0 audio processor timer 1 usb controller nf controller spi interface mmc controller keyboard data flow controller serial i/o port psi interface
58 AT85C51SND3bx 7632a?mp3?03/06 external interrupts int1:0 inputs external interrupts int0 and int1 ( intn , n = 0 or 1) pins may each be programmed to be level-triggered or edge-triggered, dependent upon bits it0 and it1 ( itn , n = 0 or 1) in tcon register as shown in int1:0 input circuitry . if itn = 0, intn is triggered by a low level at the pin. if itn = 1, intn is negative-edge triggered. external interrupts are enabled with bits ex0 and ex1 ( exn , n = 0 or 1) in ien0. events on intn set the inter - rupt request flag ien in tcon register. if the interrupt is edge-triggered, the request flag is cleared by hardware when vectoring to the interrupt service routine. if the interrupt is level-triggered, the interrupt service routine must clear the request flag and the interrupt must be de-asserted before the end of the interrupt service routine. int0 and int1 inputs provide both the capability to exit from power-down mode on low level signals as detailed in section ?exiting power-down mode?, page 21 . figure 29. int1:0 input circuitry kin3:0 inputs external interrupts kin0 to kin3 provide th e capability to co nnect a matrix keyboard. for detailed information on these inputs, refer to section ?keyboard interface?, page 239 . input sampling external interrupt pins ( int1:0 and kin3:0) are sampled once per peripheral cycle (6 peripheral clock periods) (see minimum pulse timings ). a level-triggered interrupt pin held low or high for more than 6 peripheral clock periods (12 oscillator in standard mode or 6 oscillator clock periods in x2 mode) guarantees detection. edge-triggered external interrupts must hold the request pin low for at least 6 peripheral clock periods. figure 30. minimum pulse timings 0 1 int0/1 it0/1 tcon.0/2 ex0/1 ien0.0/2 int0/1 interrupt request ie0/1 tcon.1/3 edge-triggered interrupt level-triggered interrupt 1 cycle 1 cycle > 1 peripheral cycle 1 cycle > 1 peripheral cycle
59 AT85C51SND3bx 7632a?mp3?03/06 registers reset value = 0000 0000b table 72. ien0 register ien0 (0.a8h) ? interrupt enable register 0 7 6 5 4 3 2 1 0 ea eaup edfc es et1 ex1 et0 ex0 bit number bit mnemonic description 7 ea enable all interrupt bit set to enable all interrupts. clear to disable all interrupts. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 eaup aup interrupt enable bit set to enable audio processor interrupt. clear to disable audio processor interrupt. 5 edfc dfc enable bit set to enable data flow interrupt. clear to disable data flow interrupt. 4 es sio interrupt enable bit set to enable serial port interrupt. clear to disable serial port interrupt. 3 et1 t1 overflow interrupt enable bit set to enable timer 1 overflow interrupt. clear to disable timer 1 overflow interrupt. 2 ex1 ex1 interrupt enable bit set to enable external interrupt 1. clear to disable external interrupt 1. 1 et0 t0 overflow interrupt enable bit set to enable timer 0 overflow interrupt. clear to disable timer 0 overflow interrupt. 0 ex0 ex0 interrupt enable bit set to enable external interrupt 0. clear to disable external interrupt 0.
60 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 73. ien1 register ien1 (0.b1h) ? interrupt enable register 1 76543210 - - emmc enfc espi epsi ekb eusb bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 emmc mmc/sd interrupt enable bit set to enable mmc/sd interrupt. clear to disable mmc/sd interrupt. 4enfc nfc interrupt enable bit set to enable ide interrupt. clear to disable ide interrupt. 3 espi spi interrupt enable bit set to enable spi interrupt. clear to disable spi interrupt. 2 epsi psi interrupt enable bit set to enable psi interrupt. clear to disable psi interrupt. 1ekb kbd interrupt enable bit set to enable keyboard interrupt. clear to disable keyboard interrupt. 0eusb usb interrupt enable bit set this bit to enable usb interrupt. clear this bit to disable usb interrupt.
61 AT85C51SND3bx 7632a?mp3?03/06 reset value = x000 0000b table 74. iph0 register iph0 (0.b7h) ? interrupt priority high register 0 7 6 5 4 3 2 1 0 - iphaup iphdfc iphs ipht1 iphx1 ipht0 iphx0 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 iphaup aup interrupt priority level msb refer to ta b l e 70 for priority level description. 5 iphdfc dfc interrupt priority level msb refer to ta b l e 70 for priority level description. 4 iphs sio interrupt priority level msb refer to ta b l e 70 for priority level description. 3 ipht1 t1 interrupt priority level msb refer to ta b l e 70 for priority level description. 2 iphx1 ex1 interrupt priority level msb refer to ta b l e 70 for priority level description. 1 ipht0 t0 interrupt priority level msb refer to ta b l e 70 for priority level description. 0 iphx0 ex0 interrupt priority level msb refer to ta b l e 70 for priority level description.
62 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 75. iph1 register iph1 (0.b3h) ? interrupt priority high register 1 7 6 5 4 3 2 1 0 - - iphmmc iphnfc iphspi iphspi iphkb iphusb bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 iphmmc mmc/sd interrupt priority level msb refer to ta b l e 70 for priority level description. 4 iphnfc nfc interrupt priority level msb refer to ta b l e 70 for priority level description. 3 iphspi spi interrupt priority level msb refer to ta b l e 70 for priority level description. 2 iphpsi psi interrupt priority level msb refer to ta b l e 70 for priority level description. 1 iphkb kbd interrupt priority level msb refer to ta b l e 70 for priority level description. 0 iphusb usb interrupt priority level msb refer to ta b l e 70 for priority level description.
63 AT85C51SND3bx 7632a?mp3?03/06 reset value = x000 0000b table 76. ipl0 register ipl0 (0.b8h) - interrupt priority low register 0 7 6 5 4 3 2 1 0 - iplaup ipldfc ipls iplt1 iplx1 iplt0 iplx0 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 iplaup aup interrupt priority level lsb refer to ta b l e 70 for priority level description. 5 ipldfc dfc interrupt priority level lsb refer to ta b l e 70 for priority level description. 4 ipls sio interrupt priority level lsb refer to ta b l e 70 for priority level description. 3 iplt1 t1 interrupt priority level lsb refer to ta b l e 70 for priority level description. 2 iplx1 ex1 interrupt priority level lsb refer to ta b l e 70 for priority level description. 1 iplt0 t0 interrupt priority level lsb refer to ta b l e 70 for priority level description. 0 iplx0 ex0 interrupt priority level lsb refer to ta b l e 70 for priority level description.
64 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 77. ipl1 register ipl1 (0.b2h) ? interrupt priority low register 1 7 6 5 4 3 2 1 0 - - iplmmc iplnfc iplspi iplpsi iplkb iplusb bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 iplmmc mmc/sd interrupt priority level lsb refer to ta b l e 70 for priority level description. 4 iplnfc nfc interrupt priority level lsb refer to ta b l e 70 for priority level description. 3 iplspi spi interrupt priority level lsb refer to ta b l e 70 for priority level description. 2 iplpsi psi interrupt priority level lsb refer to ta b l e 70 for priority level description. 1 iplkb kbd interrupt priority level lsb refer to ta b l e 70 for priority level description. 0 iplusb usb interrupt priority level lsb refer to ta b l e 70 for priority level description.
65 AT85C51SND3bx 7632a?mp3?03/06 timers/counters the AT85C51SND3bx implement 2 general-pur pose, 16-bit timers/counters. they are identified as timer 0 and timer 1, and can be independently configured to operate in a variety of modes as a timer or as an event counter. when operating as a timer, the timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, the timer/counter counts negative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. the various operating modes of each timer/counter are described in the following sections. timer/counter operations for instance, a basic operation is timer registers thx and tlx (x = 0, 1) connected in cascade to form a 16-bit timer. setting the run control bit ( trx ) in tcon register (see table 81 ) turns the timer on by allowing the selected input to increment tlx . when tlx overflows it increments thx ; when thx overflows it sets the timer overflow flag ( tfx ) in tcon register. setting the trx does not clear the thx and tlx timer registers. timer registers can be accessed to obtain the current count or to enter preset values. they can be read at any time but trx bit must be cleared to preset their values, otherwise, the behavior of the timer/counter is unpredictable. the c/tx# control bit selects timer operation or counter operation by selecting the divided-down peripheral clock or external pin tx as the source for the counted signal. trx bit must be cleared when changing the mode of operation, otherwise the behavior of the timer/counter is unpredictable. for timer operation (c/tx# = 0), the timer register counts the divided-down peripheral clock. the timer register is incremented once every peripheral cycle (6 peripheral clock periods). the timer clock rate is f per /6, i.e., f osc /12 in standard mode or f osc /6 in x2 mode. for counter operation (c/tx# = 1), the time r register counts the negative transitions on the tx external input pin. the external input is sampled every peripheral cycles. when the sample is high in one cycle and low in the next one, the counter is incremented. since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is f per /12, i.e., f osc /24 in standard mode or f osc /12 in x2 mode. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. timer clock controller as shown in figure 31 , the timer 0 (ft0) and timer 1 (ft1) clocks are derived from either the peripheral clock (f per ) or the oscillator clock (f osc ) depending on the t0x2 and t1x2 bits in ckcon register. these clocks are issued from the clock controller block as detailed in section ?oscillator?, page 27 . when t0x2 or t1x2 bit is set, the timer 0 or timer 1 clock frequency is fixed and equal to the oscillator clock frequency divided by 2. when cleared, the timer clock frequency is equal to the oscillator clock fre - quency divided by 2 in standard mode or to the oscillator clock frequency in x2 mode.
66 AT85C51SND3bx 7632a?mp3?03/06 figure 31. timer 0 and timer 1 clock controller and symbols timer 0 timer 0 functions as either a timer or event counter in four modes of operation. figure 32 , figure 34 , figure 36 , and figure 38 show the logical configuration of each mode. timer 0 is controlled by the four lower bits of tmod register (see table 82 ) and bits 0, 1, 4 and 5 of tcon register (see table 81 ). tmod register selects the method of timer gating (gate0), timer or counter operation (c/t0#) and mode of operation (m10 and m00) according to table 78 . tcon register provides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and interrupt type control bit (it0). for normal timer operation (gate0 = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0 to control timer operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets tf0 flag generating an inter - rupt request. it is important to stop timer/counter before changing mode. table 78. timer/counter 0 operating modes mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (th0 reg - ister) with a modulo 32 prescaler implemented with the lower five bits of tl0 register (see figure 32 ). the upper three bits of tl0 register are indeterminate and should be ignored. prescaler overflow increments th0 register. figure 33 gives the overflow period calculation formula. per clock tim0 clock osc clock 0 1 t0x2 ckcon.1 timer 0 timer 0 clock symbol per clock tim1 clock osc clock 0 1 t1x2 ckcon.2 2 timer 1 timer 1 clock symbol clock clock 2 m10 m00 mode operation 0 0 0 8-bit timer/counter (th0) with 5-bit prescaler (tl0). 0 1 1 16-bit timer/counter. 1 0 2 8-bit auto-reload timer/counter (tl0). 1 1 3 tl0 is an 8-bit timer/counter. th0 is an 8-bit timer using timer 1?s tr0 and tf0 bits.
67 AT85C51SND3bx 7632a?mp3?03/06 figure 32. timer/counter x (x = 0 or 1) in mode 0 figure 33. mode 0 overflow period formula mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer with th0 and tl0 registers connected in cascade (see figure 34 ). the selected input increments tl0 register. figure 35 gives the overflow period calculation formula when in timer mode. figure 34. timer/counter x (x = 0 or 1) in mode 1 figure 35. mode 1 overflow period formula mode 2 (8-bit timer with auto- reload) mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from th0 register (see figure 36 ). tl0 overflow sets tf0 flag in tcon register and reloads tl0 with the contents of th0, which is preset by software. when the interrupt request is serviced, hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to th0 register. figure 37 gives the auto-reload period calculation formula when in timer mode. tfx tcon reg 0 1 gatex tmod reg overflow timer x interrup t reques t c/tx# tmod reg thx (8 bits) intx tx timx clock 6 trx tcon reg tlx (5 bits) 6 ? (16384 ? (thx, tlx)) tfx per = f timx tfx tcon reg 0 1 gatex tmod reg overflow timer x interrup t reques t c/tx# tmod reg thx (8 bits) intx tx timx clock 6 trx tcon reg tlx (8 bits) 6 ? (65536 ? (thx, tlx)) tfx per = f timx
68 AT85C51SND3bx 7632a?mp3?03/06 figure 36. timer/counter x (x = 0 or 1) in mode 2 figure 37. mode 2 auto-reload period formula mode 3 (2 x 8-bit timers) mode 3 configures timer 0 such that registers tl0 and th0 operate as separate 8-bit timers (see figure 38 ). this mode is provided for applications requiring an additional 8- bit timer or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in tmod reg - ister, and tr0 and tf0 in tcon register in the normal manner. th0 is locked into a timer function (counting f tf1 /6) and takes over use of the timer 1 interrupt (tf1) and run control (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode 3. figure 39 gives the auto-reload period calculation formulas for both tf0 and tf1 flags. figure 38. timer/counter 0 in mode 3: 2 8-bit counters figure 39. mode 3 overflow period formula tfx tcon reg overflow timer x interrup t reques t tlx (8 bits) thx (8 bits) 0 1 gatex tmod reg c/tx# tmod reg intx tx timx clock 6 trx tcon reg tfx per = f timx 6 ? (256 ? thx) tf1 tcon.7 tf0 tcon.5 0 1 gate0 tmod.3 overflow timer 0 interrup t reques t c/t0# tmod.2 intx tx tim0 clock 6 tr0 tcon.4 tl0 (8 bits) overflow timer 1 interrup t reques t th0 (8 bits) tim0 clock 6 tr1 tcon.6 tf0 per = f tim0 6 ? (256 ? tl0) tf1 per = f tim0 6 ? (256 ? th0)
69 AT85C51SND3bx 7632a?mp3?03/06 timer 0 enhanced mode timer 0 overflow period can be increased in all modes by enabling a divider as detailed in figure 40 . this mode is implemented to allow higher time periods as it can be used for example as a scheduler time base with auto-reload (mode 2). timer 0 enhanced mode is enabled by programming t0etb2:0 bits in schclk (see table 87 ) to a value other than 000b and according to table 79 . figure 40. timer/counter 0 enhanced mode table 79. timer/counter 0 enhanced overflow period timer 1 timer 1 is identical to timer 0 except for mode 3 which is a hold-count mode and for the enhanced mode which is not available. the following comments help to understand the differences: ? timer 1 functions as either a timer or event counter in three modes of operation. figure 32 , figure 34 , and figure 36 show the logical configuration for modes 0, 1, and 2. timer 1?s mode 3 is a hold-count mode. ? timer 1 is controlled by the four high-order bits of tmod register (see table 82 ) and bits 2, 3, 6 and 7 of tcon register (see table 81 ). tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and mode of operation (m11 and m01) according to table 80 . tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and interrupt type control bit (it1). ? timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. ? for normal timer operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr1 allows external pin int1 to control timer operation. ? timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag generating an interrupt request. ? when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. t0etb2 t0etb1 t0etb0 new tf0 overflow period 0 0 0 tf0 per 1 (divider disable) 0 0 1 tf0 per 2 0 1 0 tf0 per 4 0 1 1 tf0 per 8 1 0 0 tf0 per 16 1 0 1 tf0 per 32 1 1 0 tf0 per 64 1 1 1 tf0 per 128 tf0 tcon.5 timer 0 overflow t0etb2:0 schclk.6:4 2 n timer 0 interrupt request
70 AT85C51SND3bx 7632a?mp3?03/06 ? it is important to stop the timer/counter before changing modes. table 80. timer/counter 1 operating modes mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, which is set up as an 8-bit timer (th1 reg - ister) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 register (see figure 32 ). the upper 3 bits of tl1 register are ignored. prescaler overflow incre - ments th1 register. mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit timer with th1 and tl1 registers connected in cascade (see figure 34 ). the selected input increments tl1 register. mode 2 (8-bit timer with auto- reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from th1 register on overflow (see figure 36 ). tl1 overflow sets tf1 flag in tcon register and reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when tr1 run control bit is not available i.e. when timer 0 is in mode 3. interrupt each timer handles one interrupt source that is the timer overflow flag tf0 or tf1. this flag is set every time an overflow occurs. flags are cleared when vectoring to the timer interrupt routine. interrupts are enabled by setting etx bit in ien0 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register. figure 41. timer interrupt system m11 m01 mode operation 0 0 0 8-bit timer/counter (th1) with 5-bit prescaler (tl1). 0 1 1 16-bit timer/counter. 1 0 2 8-bit auto-reload timer/counter (tl1). 1 1 3 timer/counter halted. retains count. tf0 tcon.5 et0 ien0.1 timer 0 interrupt request tf1 tcon.7 et1 ien0.3 timer 1 interrupt request
71 AT85C51SND3bx 7632a?mp3?03/06 registers reset value = 0000 0000b table 81. tcon register tcon (0.88h) ? timer/counter control register 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7 tf1 timer 1 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 1 register overflows. 6 tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5 tf0 timer 0 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 0 register overflows. 4 tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3 ie1 interrupt 1 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it1). set by hardware when external interrupt is detected on int1 pin. 2 it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 ( int1 ). set to select falling edge active (edge triggered) for external interrupt 1. 1 ie0 interrupt 0 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it0). set by hardware when external interrupt is detected on int0 pin. 0 it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 ( int0 ). set to select falling edge active (edge triggered) for external interrupt 0.
72 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 82. tmod register tmod (0.89h) ? timer/counter mode control register 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int1 pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits refer to table 80 for timer 1 operation. 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0 pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1m10 timer 0 mode select bit refer to table 78 for timer 0 operation. 0m00 table 83. th0 register th0 (0.8ch) ? timer 0 high byte register 7 6 5 4 3 2 1 0 - - - - - - - - bit number bit mnemonic description 7-0 high byte of timer 0
73 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b table 84. tl0 register tl0 (0.8ah) ? timer 0 low byte register 76543210 -------- bit number bit mnemonic description 7-0 low byte of timer 0 table 85. th1 register th1 (0.8dh) ? timer 1 high byte register 7 6 5 4 3 2 1 0 - - - - - - - - bit number bit mnemonic description 7-0 high byte of timer 1 table 86. tl1 register tl1 (0.8bh) ? timer 1 low byte register 7 6 5 4 3 2 1 0 - - - - - - - - bit number bit mnemonic description 7-0 low byte of timer 1
74 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 87. schclk register schclk (0.feh) ? scheduler clocks register 76543210 - t0etb2 t0etb1 t0etb0 - - - - bit number bit mnemonic description 7- reserved the value read from this bit is always 0. do not set this bit. 6-4 t0etb2:0 timer 0 enhanced time base bits refer to table 79 for dividing values. 3-0 - reserved the value read from these bits is always 0. do not set these bits.
75 AT85C51SND3bx 7632a?mp3?03/06 watchdog timer the AT85C51SND3bx implement a hardware watchdog timer (wdt) that automati - cally resets the chip if it is allowed to time out. the wdt provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. description the wdt consists of a 14-bit prescaler followed by a 7-bit programmable counter. as shown in figure 42 , the 14-bit prescaler is fed by the wdt clock detailed in section ?clock controller? . the watchdog timer reset register (wdtrst, see table 89 ) provides control access to the wdt, while the watchdog timer program register (wdtprg, see figure 90 ) pro - vides time-out period programming. three operations control the wdt: ? chip reset clears and disables the wdt. ? programming the time-out value to the wdtprg register. ? writing a specific 2-byte 1eh-e1h sequence to the wdtrst register clears and enables the wdt. figure 42. wdt block diagram clock controller as shown in figure 43 the wdt clock (f wdt ) is derived from either the peripheral clock (f per ) or the oscillator clock (f osc ) depending on the wtx2 bit in ckcon register. these clocks are issued from the clock controller block as detailed in section ?oscillator?, page 27 . when wtx2 bit is set, the wdt clock frequency is fixed and equal to the oscillator clock frequency divided by 2. when cleared, the wdt clock frequency is equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator clock frequency in x2 mode. figure 43. wdt clock controller and symbol wto2:0 wdtprg.2:0 wdt clock 6 system 1eh-e1h decoder wdtrst 14-bit prescaler rst 7-bit counter rst to interna l en rst match set ov osc clock rs t pulse generator reset reset per clock wdt clock osc clock 0 1 wtx2 ckcon.6 2 wdt clock wdt clock symbo l
76 AT85C51SND3bx 7632a?mp3?03/06 operation after reset, the wdt is disabled. the wdt is enabled by writing the sequence 1eh and e1h into the wdtrst register. as soon as it is enabled, there is no way except the chip reset to disable it. if it is not cleared using the previous sequence, the wdt overflows and forces a chip reset. this overflow generates a low level 96 oscillator periods pulse on the rst pin to globally reset the application (refer to section ?watchdog timer reset?, page 24 ). the wdt time-out period can be adjusted using wto2:0 bits located in the wdtprg register accordingly to the formula shown in figure 44 . in this formula, wtoval repre - sents the decimal value of wto2:0 bits. table 88 reports the time-out period depending on the wdt frequency. figure 44. wdt time-out formula notes: 1. these frequencies are achieved in x1 mode or in x2 mode when wtx2 = 1: f wdt = f osc 2. 2. these frequencies are achieved in x2 mode when wtx2 = 0: f wdt = f osc . behavior during idle and power-down modes operation of the wdt during power reduction modes deserves special attention. the wdt continues to count while the cpu core is in idle mode. this means that you must dedicate some internal or external hardware to service the wdt during idle mode. one approach is to use a peripheral timer to generate an interrupt request when the timer overflows. the interrupt service routine then clears the wdt, reloads the periph - eral timer for the next service period and puts the cpu core back into idle mode. the power-down mode stops all phase clocks. this causes the wdt to stop counting and to hold its count. the wdt resumes counting from where it left off if the power- down mode is terminated by int0 , int1 or keyboard interrupt. to ensure that the wdt does not overflow shortly after exiting the power-down mode, it is recommended to clear the wdt just before entering power-down mode. the wdt is cleared and disabled if the power-down mode is terminated by a reset. table 88. wdt time-out computation wto2 wto1 wto0 wdt to (ms) / f wdt 6 mhz (1) 8 mhz (1) 10 mhz (1) 12 mhz 16 mhz (2) 20 mhz (2) 24 mhz (2) 0 0 0 16.38 12.28 9.83 8.19 6.14 4.92 4.1 0 0 1 32.77 24.57 19.66 16.38 12.28 9.83 8.19 0 1 0 65.54 49.14 39.32 32.77 24.57 19.66 16.36 0 1 1 131.07 98.28 78.64 65.54 49.14 39.32 32.77 1 0 0 262.14 196.56 157.29 131.07 98.28 78.64 65.54 1 0 1 524.29 393.1 314.57 262.14 196.56 157.29 131.07 1 1 0 1049 786.24 629.15 524.29 393.12 314.57 262.14 1 1 1 2097 1572 1258 1049 786.24 629.15 524.29 wdt to = f wdt 6 ? ( 2 14 ? 2 wtoval )
77 AT85C51SND3bx 7632a?mp3?03/06 registers reset value = xxxx xxxxb reset value = xxxx x000b table 89. wdtrst register wdtrst (0.a6h write only) ? watchdog timer reset register 7 6 5 4 3 2 1 0 - - - - - - - - bit number bit mnemonic description 7-0 - watchdog control value table 90. wdtprg register wdtprg (0.a7h) ? watchdog timer program register 7 6 5 4 3 2 1 0 - - - - - wto2 wto1 wto0 bit number bit mnemonic description 7-3 - reserved the value read from these bits is indeterminate. do not set these bits. 2-0 wto2:0 watchdog timer time-out selection bits refer to ta b l e 88 for time-out periods.
78 AT85C51SND3bx 7632a?mp3?03/06 data flow controller the data flow controller (dfc) embedded in the AT85C51SND3bx is the multimedia data transfer manager. up to two data transfers can be established through two physical data channels between a source peripheral and a destination peripheral. figure 45 shows which peripherals are connected to the internal bus which are: the cpu internal bus, the multimedia data bus and the dfc control bus. figure 45. dfc internal architecture cpu interface the dfc interfaces to the c51 core through the following special function registers: dfcon the dfc control register, dfcsta the channel status register, dfccon the channel control register, dfd0 and dfd1, the physical channel 0 and channel 1 data flow descriptor registers and dfcrc the crc data register. clock unit the dfc clock is generated based on the clock generator as detailed in section ?dfc/nfc clock generator?, page 30 . depending on the power mode (usb powered or battery powered) and the throughput desired, different clock values may be selected to control the data transfer. the dfc does not receive its system clock until dfen bit in dfcon is set, i.e. dfc enabled. data flow descriptor as shown in table 91 the data flow is characterized by a 5-byte data flow descriptor: the dfd composed of 4 fields. the data flow descriptor is written byte by byte to dfd0 (channel 0) or to dfd1 (channel 1). as soon as a dfd has been fully written, the chan - nel is enabled and data flow transfer starts when both source and destination are ready to send and receive data respectively. ram usb aup spi sio nfc mmc cpu cpu internal bus dfc control bus multimedia data bus dfc dfc clock dfen dfcon.0 psi
79 AT85C51SND3bx 7632a?mp3?03/06 table 92 shows the different peripherals (source or destination) id number. these num - bers are used to program the sid and the did in the dfd. table 91. data flow descriptor content table 92. peripheral id number crc processor in order to verify integrity of data transfe rred through the dfc, a crc calculation can be enabled using dfcrcen bit in dfcon. it cons ists in a 16-bit crc which is the remain - der after transfer data (msb first) is divided by g(x). polynomial formula is: g(x) = x 16 + x 15 + x 2 + 1. crc16 operates on channel 0 only. after an hardware reset, the crc value is 0x 0000 but can be set to any initial value by writing two bytes (1) (msb first) in the dfcrc register. at the end of the data flow transfer (2) , crc is available to user by reading two bytes (1) (msb first) from the dfcrc register. notes: 1. this double write or read sequence can be reset by clearing the crcen bit. 2. the crc value is not reset at start-up of a new data transfer. null device the null device is used to allow crc calculation on some data transfer (see section ?crc processor? ). when selected as destination, the null device is always ready and simply acknowledges and discards data coming from the source. when byte number byte mnemonic description 0 sid source identifier see table 92 for peripheral id number. 1 did destination identifier see table 92 for peripheral id number. 2 dps data packet size decimal value giving the packet size as 2 dps . dps takes value from 0 (1-byte packet size) to 13 (8192-byte packet size). packet size is limited to 8192 bytes in case of dps value greater than 13 3 dfsh data flow size 16-bit wide data leading to data flow size from 1 to 2 16 - 1 data packets. writing 0x0000 to this field enables continuous data flow. 4 dfsl id number peripheral 0 c51 ram 1 usb controller 2 audio controller 1 3 audio controller 2 4 psi controller 5 spi controller 6 sio controller 7 nand flash controller 8 mmc/sd controller 9 n 14 reserved 15 null device
80 AT85C51SND3bx 7632a?mp3?03/06 selected as source, the null device is always ready and sends the data (2 bytes) of the initialized crc value msb first. channel priority the data flow controller bandwidth is shared between channel 0 and channel 1. in case both channels are ready to transfer data, bus bandwidth is shared on a byte by byte basis. in order to allocate maximum bandwidth to a specified channel, priority can be assigned to channel 0 or to channel 1 by setting the dfprio1:0 bits in dfcon according to table 93 . dfprio1:0 can be modified at any time while transfer is on-going or not. table 93. channel priority assignment data flow status an on-going data flow transfer is reported to user using the bits df bsy0 and dfbsy1 in dfcsta. these bits are set as soon as the dfd has been fully written to the corre - sponding channel and cleared at the end of transfer or abort. source peripheral and destination peripheral status is dynamically reported by srdy0, drdy0, srdy1, drdy1 ready flags in dfcsta. data flow abort the dfc allows asynchronous abort of any on-going flow. abort is controlled by the dfabt0, dfabt1, the channel data flow abort control bits in dfccon and dfabtm the data flow abort mode control bit in dfcon. setting dfabt0 or dfabt1 while a flow transfer is on-going triggers on the correspond - ing channel an immediate or delayed abort depending on the dfabtm value. dfabtm cleared triggers an immediate abort where data flow transfer is stopped at the end of the on-going byte transfer while dfabtm set triggers a delayed abort where data flow transfer is stopped at the end of the on-going data packet transfer. above abort modes set the end of flow interrupt flag of the corresponding channel. setting dfabt0 or dfabt1 while a dfd is under writing will reset the dfd content of the corresponding channel. such abort does not set the end of flow interrupt flag of the corresponding channel. abort status in case a data flow transfer is aborted, the remaining number of data packets to be transmitted can be retrieved by reading two bytes with msb first from the data flow descriptor register dfd0 (channel 0) or to dfd1 (channel 1). this feature is of interest in case of logical data flow management over a physical channel. note: in case of immediate abort, returned value is not significant since part of the dp is already transmitted. dfprio1 dfprio0 assignment description 0 0 no priority assigned: channel 0 & channel 1 have same priority. 0 1 priority assigned to channel 0. 1 0 priority assigned to channel 1. 1 1 reserved, do not set both bits.
81 AT85C51SND3bx 7632a?mp3?03/06 figure 46. immediate data flow abort diagram figure 47. delayed data flow abort diagram data flow configuration prior to any operation, the dfc must be configured in term of clock source and channel priority, then dfc can be enabled. each time a data flow must be established, a data flow descriptor must be written to the dfc. interrupts as shown in figure 48 , the dfc interrupt request is generated by 2 different sources: the eofi0 flag or eofi1 flag in dfcsta. both sources can be enabled separately by using the eofe0 and eofe1 bits in dfccon. a global enable of the dfc interrupt is provided by setting the edfc bit in ienx register. the interrupt is requested each time one of the 2 sources is asserted. eofi0 or eofi1 flags are set: ? at the end of a data flow on respective channel. ? after an immediate abort command at the end of the byte transfer. ? after a delayed abort at the end of the data packet transfer. note: an abort command never sets flags while in the process of writing dfd. eofi0 and eofi1 flags must be cleared by software by setting eofia0 and eofia1 bits in dfccon, in order to acknowledge the interrupt. setting these flags by software has no effect. figure 48. dfc interrupt system data bus dfabtx dfbsyx dp remaining dp n+1 n n+2 data bus dfabtx dfbsyx dp dp remaining dp n+1 n n+2 eofi1 dfcsta.5 dfc interrupt request eofi0 dfcsta.1 eofe1 dfccon.6 edfc ienx.y eofe0 dfccon.2
82 AT85C51SND3bx 7632a?mp3?03/06 registers reset value = 0000 0000b table 94. dfcon register dfcon ( 1.89h ) ? dfc control register 7 6 5 4 3 2 1 0 - dfres - dfcrcen dfprio1 dfprio0 dfabtm dfen bit number bit mnemonic description 5 - reserved the value read from this bit is always 0. do not set this bit. 6 dfres data flow controller reset bit set then clear this bit to reset the data flow controller by software. 5 - reserved the value read from this bit is always 0. do not set this bit. 4 dfcrcen crc enable bit set to enable crc calculation on channel 0. clear to disable crc calculation. 3-2 dfprio1:0 data flow channel priority assignment bits refer to table 93 for channel priority assignment description. 1 dfabtm data flow abort mode bit set to trigger a delayed abort. clear to trigger an immediate abort. 0 dfen data flow controller enable bit set to enable the data flow controller. clear to disable the data flow controller. table 95. dfcsta register dfcsta ( 1.88h bit addressable ) ? dfc channel status register 7 6 5 4 3 2 1 0 drdy1 srdy1 eofi1 dfbsy1 drdy0 srdy0 eofi0 dfbsy0 bit number bit mnemonic description 7 drdy1 channel 1 destination ready flag set by hardware when the destination peripheral of channel 1 is ready. cleared by hardware when the destination peripheral of channel 1 is not ready. 6 srdy1 channel 1 source ready flag set by hardware when the source peripheral of channel 1 is ready. cleared by hardware when the source peripheral of channel 1 is not ready. 5 eofi1 channel 1 end of data flow interrupt flag set by hardware at the end of a channel 1 data flow transfer. cleared by software by setting eofia1 in dfccon. can not be set by software. 4 dfbsy1 channel 1 busy flag set by hardware when a transfer is on-going on channel 1. cleared by hardware when no transfer is on-going on channel 1.
83 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b 3 drdy0 channel 0 destination ready flag set by hardware when the source peripheral of channel 0 is ready. cleared by hardware when the source peripheral of channel 0 is not ready. 2 srdy0 channel 0 source ready flag set by hardware when the destination peripheral of channel 0 is ready. cleared by hardware when the destination peripheral of channel 0 is not ready. 1 eofi0 channel 0 end of data flow interrupt flag set by hardware at the end of a channel 0 data flow transfer. cleared by software by setting eofia0 in dfccon. can not be set by software. 0 dfbsy0 channel 0 busy flag set by hardware when a transfer is on-going on channel 0. cleared by hardware when no transfer is on-going on channel 0. table 96. dfccon register dfccon ( 1.85h ) ? dfc channel control register 7 6 5 4 3 2 1 0 dfabt1 eofe1 eofia1 - dfabt0 eofe0 eofia0 - bit number bit mnemonic description 7 dfabt1 channel 1 abort control bit set to trigger an abort on channel 1. this bit is cleared by hardware. 6 eofe1 channel 1 end of data flow interrupt enable bit set to enable channel 1 eof interrupt. clear to disable channel 1 eof interrupt. 5 eofia1 channel 1 end of flow interrupt acknowledge bit set to acknowledge the channel 1 eof interrupt (clear eofi1 flag). clearing this bit has no effect. the value read from this bit is always 0. 4 - reserved the value read from this bit is always 0. do not set this bit. 3 dfabt0 channel 0 abort control bit set to trigger an abort on channel 0. this bit is cleared by hardware. 2 eofe0 channel 0 end of data flow interrupt enable bit set to enable channel 0 eof interrupt. clear to disable channel 0 eof interrupt. 1 eofia0 channel 0 end of flow interrupt acknowledge bit set to acknowledge the channel 0 eof interrupt (clear eofi0 flag). clearing this bit has no effect. the value read from this bit is always 0. 0 - reserved the value read from this bit is always 0. do not set this bit. bit number bit mnemonic description
84 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b table 97. dfd0 register dfd0 ( 1.8ah ) ? dfc channel 0 data flow descriptor register 7 6 5 4 3 2 1 0 dfd0d7 dfd0d6 dfd0d5 dfd0d4 dfd0d3 dfd0d2 dfd0d1 dfd0d0 bit number bit mnemonic description 7-0 dfd0d7:0 channel 0 data flow descriptor data write data flow descriptor to this register as detailed in table 91 . read to get the remaining number of data packet after a delayed abort. msb is read first. table 98. dfd1 register dfd1 ( 1.8bh ) ? dfc channel 1 data flow descriptor register 7 6 5 4 3 2 1 0 dfd1d7 dfd1d6 dfd1d5 dfd1d4 dfd1d3 dfd1d2 dfd1d1 dfd1d0 bit number bit mnemonic description 7-0 dfd1d7:0 channel 1 data flow descriptor data write data flow descriptor to this register as detailed in table 91 . read to get the remaining number of data packet after a delayed abort. msb is read first. table 99. dfcrc register dfcrc ( 1.8ch ) ? dfc crc data register 7 6 5 4 3 2 1 0 crcd7 crcd6 crcd5 crcd4 crcd3 crcd2 crcd1 crcd0 bit number bit mnemonic description 7-0 crcd7:0 crc 2-byte data fifo first reading of dfcrc returns the msb of the crc16 data while second reading returns the lsb. first writing to dfcrc writes the msb of the initial value of the crc16 data while second writing writes the lsb.
85 AT85C51SND3bx 7632a?mp3?03/06 usb controller the AT85C51SND3bx implements a usb controller allowing the AT85C51SND3bx to act as a usb device or a usb host. the main features of the usb controller: ? full-speed and high-speed device. ? full-speed host with otg compliance. ? automatic data flow controller (dfc) transfer without cpu support. ? 2368 bytes of dpram. ? up to 7 endpoints/pipes ? 1 endpoint of 64 bytes (default control), ? 2 endpoints of 512 bytes max, (one or two banks), ? 4 endpoints of 64 bytes max, (one or two banks). description the c51 core interfaces with the usb controller using a set of special function registers detailed in table 49, page 39 . as shown in figure 49 , the usb controller is based on seven functional blocks: ? the pll clock (see section ?clock generator?, page 28 ) which delivers 480 mhz clock for usb high-speed mode support. ? the usb hs/fs pad supporting speed negotiation, attach/detach and data transfer ? the usb otg pad supporting otg negotiation ? the device controller allowing AT85C51SND3b to act as a device ? the host controller allowing AT85C51SND3b to act as a device ? the 2368-byte dual port ram for endpoints and pipes memory ? the interrupt controller figure 49. usb controller block diagram usb connection figure 50 shows the connection of the AT85C51SND3b to the usb connector and the the connection of the rc filter to the ubias pin. dpf and dmf pins are connected through 2 termination resistors. value of all discrete components is detailed in the section ?dc characteristics?, page 241 . uvcc uid dpf dmf dph ubias dmh pll clock full speed high speed device controller host controller otg usb pad usb pad usb interrupt request 2368 bytes dpram interrupt controller uvcon dfc bus cpu bus
86 AT85C51SND3bx 7632a?mp3?03/06 figure 50. usb connection general operating modes introduction after a hardware reset, the usb controller is disabled. when enabled, the usb controller has to run the device controller or the host control - ler. this is performed using the id detection. ? if the id pin is not connected to ground, the id bit is set by hardware (internal pull up on the uid pad) and the usb device controller is selected. ? the id bit is cleared by hardware when a low level has been detected on the id pin. the device controller is then disabled and the host controller enabled. the software anyway has to select the mode (host, device) in order to access to the device controller registers or to the host controller registers, which are multiplexed. for example, even if the usb controller has detected a device mode (pin id high), the soft - ware shall select the device mode (bit host cleared), otherwise it will access to the host registers. this is also true for the host mode. power-on and reset figure 51 shows the usb controller main states after power-on. figure 51. usb controller reset state machine usb controller state after an hardware reset is ?reset?. in this state: ? usbe is not set, ? the macro clock is stopped in order to minimize the power consumption (frzclk=1), ? the macro is disabled, ? the pad is in the suspend mode, ? the host and device usb controllers internal states are reset. dph dmh vbus gnd d+ d- r uft uvcc dpf dmf r uft ubias c ub r ub uvss vss uid id otg 5v generator uvcon on out dev ice reset usbe=0 usbe=1 id=1 clock stopped frzclk=1 mac ro off usbe=0 usbe=0 host usbe=0 hw reset usbe=1 id=0
87 AT85C51SND3bx 7632a?mp3?03/06 ? the dpacc bit and the dpadd10:0 field can be set by software. the dpram is not cleared. ? the spdconf bits can be set by software. after setting usbe, the usb controller enters in the host or in the device state (accord - ing to the uid pin level). the selected controller is ?idle?. the usb controller can at any time be ?stopped? by clearing usbe. in fact, clearing usbe acts as an hardware reset. interrupts as shown in figure 52 , the usb controller implements five main global interrupt sources: the usb general and otg interrupts detailed in figure 53 , the usb device and endpoint interrupts detailed in section ?interrupts?, page 113 , and the usb host and pipe interrupts detailed in section ?interrupt?, page 134 . figure 52. usb interrupt system figure 53. usb general and otg interrupt system usb controller interrupt request usb general & otg interrupt usb device interrupt endpoint interrupt usb host interrupt pipe interrupt eusb ien1.0 vbusti usbint.0 vbuste usbcon.0 bcerri otgint.2 bcerre otgien.2 roleexi otgint.3 roleexe otgien.3 stoi otgint.5 stoe otgien.5 idti usbint.1 idte usbcon.1 vberri otgint.1 vberre otgien.1 srpi otgint.0 srpe otgien.0 hnperri otgint.4 hnperre otgien.4 usb general & otg interrupt
88 AT85C51SND3bx 7632a?mp3?03/06 there are 2 kinds of interrupts: processing (i.e. their generation are part of the normal processing) and exception (errors). processing interrupts are generated when the following events are triggered: ? idti: id pad detection (insert, remove) ? vbusti: vbus plug-in detection (insert, remove) ? srpi: srp detected ? roleexi: role exc hanged exception interrupts are generated when the following events are triggered: ? vberri: drop on vbus detected ? bcerri: error during the b-connection ? hnperri: hnp error ? stoi: time-out detected during suspend mode power modes idle mode in this mode, the cpu core is halted (cpu clock stopped). the idle mode is taken regardless of the usb controller state (running or not). the cpu wakes up on any usb interrupts. power down in this mode, the oscillator and pll are stopped and the cpu and peripherals are fro - zen. the cpu ?wakes up? when: ? the wakeupi interrupt is triggered in the peripheral mode (host cleared), ? the rxrsmi or the srpi interrupt is triggered in the host mode (host set). ? the idti interrupt is triggered ? the vbusti interrupt is triggered freeze clock the firmware has the ability to reduce the power consumption by setting the frzclk bit, which freezes the clock of usb controller. when frzclk is set, it is still possible to have an access to the following registers: ? usbcon, usbsta, usbint ? dpram direct access (dpadd10:0, uxdatx) ? udcon (detach, ?) ? udint ? udien ? uhcon ? uhint ? uhien moreover, when frzclk is set, only the following interrupts may be triggered: ? wakeupi ?idti ? vbusti
89 AT85C51SND3bx 7632a?mp3?03/06 speed control device mode when the usb interface is configured in device mode, the speed selection (full speed or high speed) is performed automatically by the usb controller during the usb reset. a the end of the usb reset, the usb controller automatically enables or disables high- speed terminations and pull-up. note: it is possible to force the speed of the protocol, through the spdconf1:0 bits. for nor - mal operations, spdconf1:0 must be cleared. for all other operations (e.g. running in full-speed only), spdconf1:0 shall be written before enabling the controller (usbe set), in order to avoid any side effects. the follow - ing table summarizes all the possible configurations: table 100. speed configuration clearing usbe resets spdconf1:0. host mode when the usb interface is configured in host mode, internal pull down resistors are acti - vated on both dmf and dpf lines. memory access capability the cpu has the capability to directly access to the usb internal memory (dpram). the memory access mode is performed using udpaddh and udpaddl registers. to enter in this mode: ? usbe bit must be cleared. ? dpacc bit and the base address dpadd10:0 must be set. the dpacc bit and dpadd10:0 field can be used by the firmware even if the usbe bit is cleared. then, a read or a write in uedatx (device mode) or in updatx (host mode) is per - formed according to dpadd10:0 and the base address dpadd10:0 field is automatically increased. the endpoint fifo pointers and the value of the uxnum regis - ters are discarded in this mode. the aim of this functionality is to use the dpram as extra-memory. mode spdconf1:0 description peripheral 00 normal mode (default) use high-speed pad in full-speed or high-speed. 01 full-speed only mode (full-speed pad) shall be done before setting usbe. 10 high-speed only mode (high-speed pad) shall be used in debug mode. 11 full-speed only mode (high-speed pad) host xx use full-speed pad
90 AT85C51SND3bx 7632a?mp3?03/06 when using this mode, there is no influence over the usb controller. memory management the controller only supports the following memory allocation management: the reservation of a pipe or an endpoint can only be made in the growing order (pipe/endpoint 0 to the last pipe/endpoint). the firmware shall thus configure them in the same order. the reservation of a pipe or an endpoint ?k i ? is done when its alloc bit is set. then, the hardware allocates the memory and insert it between the pipe/endpoints ?k i-1 ? and ?k i+1 ?. the ?k i+1 ? pipe/endpoint memory ?slides? up and its data is lost. note that the ?k i+2 ? and upper pipe/endpoint memory does not slide. clearing a pipe enable (pen) or an endpoint enable (epen) does not clear neither its alloc bit, nor its configuration (epsize/psize, epbk/pbk). to free its memory, the firmware should clear alloc. then, the ?k i+1 ? pipe/endpoint memory automatically ?slides? down. note that the ?k i+2 ? and upper pipe/endpoint memory does not slide. the following figure illustrates the allocation and reorganization of the usb memory in a typical example: figure 54. allocation and reorganization usb memory flow endpoint 0 endpoint 1 to n unused [dpaddh ? dpaddl] usb dpram free memory 0 1 2 3 4 5 epen=1 alloc=1 free memory 0 1 2 4 5 epen=0 (alloc=1) free memory 0 1 2 4 5 pipe/endpoints activation pipe/endpoint disable free its memory (alloc=0) free memory 0 1 2 3 (bigger size) 5 pipe/endpoint activatation lost memory 4 conflic t
91 AT85C51SND3bx 7632a?mp3?03/06 ? first, pipe/endpoint 0 to pipe/endpoint 5 are configured, in the growing order. the memory of each is reserved in the dpram. ? then, the pipe/endpoint 3 is disabled ( epen=0), but its memory reservation is internally kept by the controller. ? its alloc bit is cleared: the pipe/endpoint 4 ?slides? down, but the pipe/endpoint 5 does not ?slide?. ? finally, if the firmware chooses to reconfigure the pipe/endpoint 3, with a bigger size. the controller reserved the memory after the endpoint 2 memory and automatically ?slide? the pipe/endpoint 4. the pipe/endpoint 5 does not move and a memory conflict appear, in that both pipe/endpoint 4 and 5 use a common area. the data of those endpoints are potentially lost. notes: 1. the data of pipe/endpoint 0 are never lost whatever the activation or deactivation of the higher pipe/endpoint. its data is lost if it is deactivated. 2. deactivate and reactivate the same pipe/endpoint with the same parameters does not lead to a ?slide? of the higher endpoints. for those endpoints, the data are preserved. 3. cfgok is set by hardware even in the case that there is a ?conflict? in the memory allocation. pad suspend figure 55 and figure 56 illustrate the pad behaviour: ? in the ?idle? mode, the pad is put in low power consumption mode. ? in the ?active? mode, the pad is working. figure 55. pad behaviour state machine the suspi flag indicates that a suspend state has been detected on the usb bus. this flag automatically puts the usb pad in idle state. the detection of a non-idle event sets the wakeupi flag and wakes-up the usb pad. figure 56. pad behavior waveforms moreover, the pad can also be put in the ?idle? mode if the detach bit is set. it come back in the active mode when the detach bit is cleared. idle mode active mode usbe=1 & detach=0 & suspend usbe=0 | detach=1 | suspend pad status wakeupi suspi active active idle suspend detected pad => idle state resume detected pad => active state clear resume by software clear suspend by software
92 AT85C51SND3bx 7632a?mp3?03/06 otg timers customizing it is possible to refine some otg timers thanks to the otgtcon register (see table 108 ). this register is multiplexed with the otgcon register. the timers are as defined in the otg specification: ? awaitvrise time-out. [otg] chapter 6.6.5.1 ? vbbuspulsing . [otg] chapter 5.3.4 ? pdtmoutcnt . [otg] chapter 5.3.2 ? srpdettmout . [otg] chapter 5.3.3 table 101. otg timer configuration plug-in detection the usb connection is detected by the vbus pad, thanks to the following architecture: figure 57. plug-in detection input block diagram pag e 1:0 val ue2 :0 timing parameter 00 00 awaitvrise time-out = 20 ms. 01 awaitvrise time-out = 50 ms. 10 awaitvrise time-out = 70 ms. 11 awaitvrise time-out = 100 ms. 01 00 vbbuspulsing = 15 ms. 01 vbbuspulsing = 23 ms. 10 vbbuspulsing = 31 ms. 11 vbbuspulsing = 40 ms. 10 00 pdtmoutcnt = 96 ms. 01 pdtmoutcnt = 105 ms. 10 pdtmoutcnt = 118 ms. 11 pdtmoutcnt = 131 ms. 11 00 srpdettmout = 10 s. 01 srpdettmout = 100 s. 10 srpdettmout = 1 ms. 11 srpdettmout = 11 ms. vbusti usbint.0 uvcc vbus usbsta.0 vss vdd pad logic logic session_valid va_vbus_valid r pu r pu vbus_pulsing vbus_discharge
93 AT85C51SND3bx 7632a?mp3?03/06 the control logic of the uvcc pad outputs 2 signals: ? the ?session_valid? signal is active high when the voltage on the uvcc pin is higher or equal to 1.4v. ? the ?va_vbus_valid? signal is active high when the voltage on the uvcc pin is higher or equal to 4.4v. in the host mode, the vbus flag follows the next hysteresis rule: ? vbus is set when the voltage on the uvcc pin is higher or equal to 4.4 v. ? vbus is cleared when the voltage on the uvcc pin is lower than 1.4 v. in the peripheral mode, the vbus flag follows the next rule: ? vbus is set when the voltage on the uvcc pin is higher or equal to 1.4 v. ? vbus is cleared when the voltage on the uvcc pin is lower than 1.4 v. the vbusti interrupt is triggered at each transition of the vbus flag.
94 AT85C51SND3bx 7632a?mp3?03/06 id detection the id pin transition is detected thanks to the following architecture: figure 58. id detection input block diagram by default, (no a-plug or b-plug), the macro is in the peripheral mode (internal pull-up). the idti interrupt is triggered when a a-plug (host) is plugged or unplugged. the inter - rupt is not triggered when a b-plug (peripheral) is plugged or unplugged. the idti interrupt may be triggered even if the usb controller is disabled. registers usb general registers r pu uid id usbsta.1 internal pull up vdd idti usbint.1 table 102. usbcon register usbcon ( 1.e1h ) ? usb general control register 7 6 5 4 3 2 1 0 usbe host frzclk otgpade - - idte vbuste bit number bit mnemonic description 7 usbe usb controller enable bit set to enable the usb controller. clear to disable and reset the usb controller, to disable the usb transceiver and to disable the usb controller clock inputs. 6 host host bit set to access to the host registers. clear to access to the device registers. 5 frzclk freeze usb clock bit set to disable the clock inputs (the ?resume detection? is still active) and save power consumption. clear to enable the clock inputs. 4 otgpade otg pad enable set to enable the otg pad. clear to disable the otg pad. note that this bit can be set/cleared even if usbe= 0 (this allows the vbus detection even if the usb macro is disable). 3-2 - reserved the value read from these bits is always 0. do not set these bits. 1 idte id transition interrupt enable bit set this bit to enable the id transition interrupt generation. clear this bit to disable the id transition interrupt generation.
95 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0010 0000b reset value = 0000 0000b reset value = 0000 0000b 0 vbuste vbus transition interrupt enable bit set this bit to enable the vbus transition interrupt generation. clear this bit to disable the vbus transition interrupt generation. table 103. usbsta register usbsta ( 1.e2h ) ? usb general status register 7 6 5 4 3 2 1 0 - - - - - speed id vbus bit number bit mnemonic description 7-3 - reserved the value read from these bits is always 0. do not set these bits. 2 speed speed status flag set by hardware when the controller is in high-speed mode. cleared by hardware when the controller is in full-speed mode. 1 id iud pin flag set / cleared by hardware and reflects the state of the uid pin. 0 vbus vbus flag set / cleared by hardware and reflects the level of the uvcc pin. see section ?plug-in detection? for more details. table 104. usbint register usbint ( 1.e3h ) ? usb global interrupt register 7 6 5 4 3 2 1 0 - - - - - - idti vbusti bit number bit mnemonic description 7-2 - reserved the value read from these bits is always 0. do not set these bits. 1 idti id transition interrupt flag set by hardware when a transition (high to low, low to high) has been detected on the uid pin. shall be cleared by software. 0 vbusti vbus transition interrupt flag set by hardware when a transition (high to low, low to high) has been detected on the uvcc pin. shall be cleared by software. bit number bit mnemonic description
96 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 105. udpaddh register udpaddh ( 1.e4h ) ? usb dual port ram direct access high register 7 6 5 4 3 2 1 0 dpacc - - - - dpadd10:8 bit number bit mnemonic description 7 dpacc dpram direct access bit set this bit to directly read the content the dual-port ram (dpr) data through the uedatx or updatx registers. see section ?memory access capability? for more details. clear this bit for normal operation and access the dpr through the endpoint fifo. 6-3 - reserved the value read from these bits is always 0. do not set these bits. 2-0 dpadd10:8 dpram address high bit dpadd10:8 is the most significant part of dpadd. the least significant part is provided by the udpaddl register. table 106. udpaddl register udpaddl ( 1.e5h ) ? usb dual port ram direct access high register 7 6 5 4 3 2 1 0 dpadd7:0 bit number bit mnemonic description 7-0 dpadd7:0 dpram address low bit dapdd7:0 is the least significant part of dpadd. the most significant part is provided by the udpaddh register. table 107. otgcon register otgcon ( 1.e6h ) ? usb otg control register 7 6 5 4 3 2 1 0 0 - hnpreq srpreq srpsel vbushwc vbusreq vbusrqc bit number bit mnemonic description 7 0 otgcon pagination this bit must be cleared to access the otgcon register. 6 - reserved the value read from these bits is always 0. do not set these bits.
97 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b 5 hnpreq hnp request bit set to initiate the hnp when the controller is in the device mode (b). set to accept the hnp when the controller is in the host mode (a). cleared by hardware after the hnp completion. 4 srpreq srp request bit set to initiate the srp when the controller is in device mode. cleared by hardware when the controller is initiating a srp. 3 srpsel srp selection bit set to choose vbus pulsing as srp method. clear to choose data line pulsing as srp method. 2 vbushwc vbus hardware control bit set to disable the hardware control over the uvcon pin. clear to enable the hardware control over the uvcon pin. 1 vbusreq vbus request bit set to assert the uvcon pin in order to enable the vbus power supply generation. this bit shall be used when the controller is in the host mode. cleared by hardware when vbusrqc is set. 0 vbusrqc vbus request clear bit set to deassert the uvcon pin in order to enable the vbus power supply generation. this bit shall be used when the controller is in the host mode. cleared by hardware immediately after the set. table 108. otgtcon register otgtcon ( 1.e6h ) ? usb otg timer control register 7 6 5 4 3 2 1 0 1 page1:0 - - value2:0 bit number bit mnemonic description 7 1 otgtcon pagination this bit must be set to access the otgtcon register. 6-5 page1:0 timer page access bit set/clear to access a special timer register. see section ?otg timers customizing? for more details. 4-3 - reserved the value read from these bits is always 0. do not set these bits. 2-0 value2:0 value bit set to initialize the new value of the timer. see section ?otg timers customizing? for more details. bit number bit mnemonic description
98 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 109. otgien register otgien ( 1.e7h ) ? usb otg interrupt enable register 7 6 5 4 3 2 1 0 - - stoe hnperre roleexe bcerre vberre srpe bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 stoe suspend time-out error interrupt enable bit set to enable the stoi interrupt. clear to disable the stoi interrupt. 4 hnperre hnp error interrupt enable bit set to enable the hnperri interrupt. clear to disable the hnperri interrupt. 3 roleexe role exchange interrupt enable bit set to enable the roleexi interrupt. clear to disable the roleexi interrupt. 2 bcerre b-connection error interrupt enable bit set to enable the bcerri interrupt. clear to disable the bcerri interrupt. 1 vberre vbus error interrupt enable bit set to enable the vberri interrupt. clear to disable the vberri interrupt. 0 srpe srp interrupt enable bit set to enable the srpi interrupt. clear to disable the srpi interrupt. table 110. otgint register otgint ( 1.d1h ) ? usb global interrupt register 7 6 5 4 3 2 1 0 - - stoi hnperri roleexi bcerri vberri srpi bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 stoi suspend time-out error interrupt flag set by hardware when a time-out error (more than 150 ms) has been detected after a suspend. shall be cleared by software. see for more details. 4 hnperri hnp error interrupt flag set by hardware when an error has been detected during the protocol. shall be cleared by software. see for more details.
99 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b 3 roleexi role exchange interrupt flag set by hardware when the usb controller has successfully swapped its mode, due to an hnp negotiation: host to device or device to host. shall be cleared by software. see for more details. 2 bcerri b-connection error interrupt flag set by hardware when an error occur during the b-connection. shall be cleared by software. 1 vberri v-bus error interrupt flag set by hardware when a drop on vbus has been detected. shall be cleared by software. 0 srpi srp interrupt flag set by hardware when a srp has been detected. shall be used in the host mode only. shall be cleared by software. bit number bit mnemonic description
100 AT85C51SND3bx 7632a?mp3?03/06 usb software operating modes depending on the usb operating mode, the software should perform some of the follow - ing operations: power on the usb interface ? power-on usb pads regulator ? wait usb pads regulator ready state ? configure pll interface ? enable pll ? check pll lock ? enable usb interface ? configure usb interface (usb speed, endpoints configuration...) ? wait for usb vbus information connection ? attach usb device power off the usb interface ? detach usb interface ? disable usb interface ? disable pll ? disable usb pin regulator suspending the usb interface ? clear suspend bit ? set usb suspend clock ? disable pll ? be sure to have interrupts enable to exit sleep mode ? make the mcu enter sleep mode resuming the usb interface ? enable pll ? wait pll lock ? clear usb suspend clock ? clear resume information
101 AT85C51SND3bx 7632a?mp3?03/06 usb device operating modes introduction the usb device controller supports high speed and full speed data transfers. in addition to the default control endpoint, it provides six other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: ? endpoint 0: programmable size fifo up to 64 bytes, default control endpoint. ? endpoints 1 and 2: programmable size fifo up to 512 bytes in ping-pong mode. ? endpoints 3 to 6: programmable size fifo up to 64 bytes in ping-pong mode. the controller starts in the ?idle? mode. in this mode, the pad consumption is reduced to the minimum. power-on and reset figure 59 shows the usb device controller main states after power-on. figure 59. usb device controller reset state machine the reset state of the device controller is: ? the macro clock is stopped in order to minimize the power consumption (frzclk set) ? the usb device controller internal state is reset (all the registers are reset to their default value. note that detach is set.) ? the endpoint banks are reset ? the d+ or d- pull up are not activated (mode detach) the d+ or d- pull-up will be activated as soon as the detach bit is cleared and vbus is present. the macro is in the ?idle? state after reset with a minimum power consumption and does not need to have the pll activated to enter in this state. the usb device controller can at any time be reset by clearing usbe. speed identification the high-speed reset is managed by the hardware. at the connection, the host makes a reset that can be: ? a classic reset (full-speed) or ? a high-speed reset (high-speed). reset idle hw reset usbe=0 usbe=0 usbe=1 uid=1
102 AT85C51SND3bx 7632a?mp3?03/06 at the end of the reset process (full or high), the end of reset interrupt (eorsti) is gen - erated. then the cpu should read the speed bit to know the speed mode of the device. note that the usb device controller starts in the full-speed mode after power on. endpoint reset an endpoint can be reset at any time by setting in the uerst register the bit corre - sponding to the endpoint (eprstx). this resets: ? the internal state machine on that endpoint, ? the rx and tx banks are cleared and their internal pointers are restored, ? the ueintx, uesta0x and uesta1x are restored to their reset value. the data toggle field remains unchanged. the other registers remain unchanged. the endpoint configuration remains active and the endpoint is still enabled. the endpoint reset may be associated with a clear of the data toggle command (rstdt bit) as an answer to the clear_feature usb command. usb reset when an usb reset is detected on the usb line, the next operations are performed by the controller: ? all the endpoints are disabled, except the default control endpoint, ? the default control endpoint is reset (see section ?endpoint reset? for more details). ? the data toggle of the default control endpoint is cleared. endpoint selection prior to any operation performed by the cpu, the endpoint must first be selected. this is done by: ? clearing epnums. ? setting epnum with the endpoint number which will be managed by the cpu. the cpu can then access to the various endpoint registers and data. in the same manner, if the endpoint must be accessed by the dfc, it must first be selected. this is done by: ? setting epnums. ? setting epnum with the endpoint number which will be managed by the dfc. ? setting dfcrdy when the data-flow is ready to take place. the dfc can then access to the banks (read / write). the controller internally keeps in memory the epnum for the cpu and the epnum for the dfc. in fact, there are 2 epnum registers multiplexed by the epnums bit. each of them can be read or written by the cpu. these two registers permits to easily switch from an endpoint under dfc data transfer to the default control endpoint when a setup is received, without reprogramming the epnum register: ? set epnums, ? epnum = endpoint x ? set dfcrdy when the dfc transfer is ready to take place, ? ...... ? setup received on endpoint 0 (epint0 set, rxstpi set),
103 AT85C51SND3bx 7632a?mp3?03/06 ? clear dfcrdy to freeze the dfc transfer, ? if the cpu epnum has to be changed: epnums cleared, epnum = endpoint 0 ? read endpoint 0 data (uedatx) ? set dfcrdy. this resumes the dfc transfer. endpoint activation the endpoint is maintained under reset as long as the epen bit is not set. the following flow must be respected in order to activate an endpoint: figure 60. endpoint activation flow: as long as the endpoint is not correctly configured (cfgok cleared), the hardware does not acknowledge the packets sent by the host. cfgok is will not be sent if the endpoint size parameter is bigger than the dpram size. a clear of epen acts as an e ndpoint reset (see section ?endpoint reset? for more details). it also performs the next operation: ? the configuration of the endpoint is kept ( epsize, epbk, alloc kept) ? it resets the data toggle field. ? the dpram memory associated to the endpoint is still reserved. see section ?memory management?, page 90 for more details about the memory allocation/reorganization. address setup the usb device address is set up according to the usb protocol: ? the usb device, after power-up, responds at address 0 endpoint activation cfgok=1 error no yes endpoint activated activate the endpoint select the endpoint epen=1 uenum epnum=x test the correct endpoint configuration uecfg1x alloc epsize epbk configure: - the endpoint size - the bank parametrization allocation and reorganization of the memory is made on-the-fly uecfg0x epdir eptype ... configure: - the endpoint direction - the endpoint type - the not yet disable feature
104 AT85C51SND3bx 7632a?mp3?03/06 ? the host sends a setup command (set_address(addr)), ? the firmware records that address in uadd, but keep adden cleared, ? the usb device sends an in command of 0 bytes (in 0 zero length packet), ? then, the firmware can enable the usb device address by setting adden. the only accepted address by the controller is the one stored in uadd. adden and uadd shall not be written at the same time. uadd contains the default address 00h after a power-up or usb reset. adden is cleared by hardware: ? after a power-up reset, ? when an usb reset is received, ? or when the macro is disabled (usbe cleared) when this bit is cleared, the default device address 00h is used. suspend, wake-up and resume after a period of 3 ms during which the usb line was inactive, the controller switches to the full-speed mode and triggers (if enabled) the suspi (suspend) interrupt. the firm - ware may then set the frzclk bit. the cpu can also, depending on software architecture, enter in the idle mode to lower again the power consumption. there are two ways to recover from the ?suspend? mode: ? first one is to clear the frzclk bit. this is possible if the cpu is not in the idle mode. ? second way, if the cpu is ?idle?, is to enable the wakeupi interrupt (wakeupe set). then, as soon as an non-idle signal is seen by the controller, the wakeupi interrupt is triggered. the firmware shall then clear the frzclk bit to restart the transfer. there are no relationship between the suspi interrupt and the wakeupi interrupt: the wakeupi interrupt is triggered as soon as there are non-idle patterns on the data lines. thus, the wakeupi interrupt can occurs even if the controller is not in the ?suspend? mode. when the w akeupi interrupt is tri ggered, if the suspi interrupt bit was already set, it is cleared by hardware. when the suspi interrupt is triggered, if the w akeupi interrupt bit was already set, it is cleared by hardware. detach the reset value of the detach bit is 1. it is possible to re-enumerate a device, simply by setting and clearing the detach bit. ? if the usb device controller is in full-speed mode, setting detach will disconnect the pull-up on the d+ or d- pad (depending on full or low speed mode selected). then, clearing detach will connect the pull-up on the d+ or d- pad.
105 AT85C51SND3bx 7632a?mp3?03/06 figure 61. detach a device in full-speed: remote wake-up the ?remote wake-up? (or ?upstream resume?) request is the only operation allowed to be sent by the device on its own initiative. anyway, to do that, the device should first have received a device_remote_wakeup request from the host. ? first, the usb controller must have detected the ?suspend? state of the line: the remote wake-up can only be sent after a suspi interrupt has been triggered. ? the firmware has then the ability to set rmwkup to send the ?upstream resume? stream. this will automatically be done by the controller after 5ms of inactivity on the usb line. ? when the controller starts to send the ?upstream resume?, the uprsmi interrupt is triggered (if enabled). if suspi was set, suspi is cleared by hardware. ? rmwkup is cleared by hardware at the end of the ?upstream resume?. ? if the controller detects a good ?end of resume? signal from the host, an eorsmi interrupt is triggered (if enabled). stall request for each endpoint, the stall management is performed using 2 bits: ? stallrq (enable stall request) ? stallrqc (disable stall request) ? stalli (stall sent interrupt) to send a stall handshake at the next request, the stallrq request bit has to be set. all following requests will be handshak?ed with a stall until the stallrqc bit is set. setting stallrqc automatically clears the stallrq bit. the stallrqc bit is also immediately cleared by hardware after being set by software. thus, the firmware will never read this bit as set. each time the stall handshake is sent, the stalli flag is set by the usb controller and the epintx interrupt will be triggered (if enabled). the incoming packets will be discarded (rxouti and rwal will not be set). the host will then send a command to reset the stall: the firmware just has to set the stallrqc bit and to reset the endpoint. special consideration for control endpoints a setup request is always ack?ed. if a stall request is set for a control endpoint and if a setup request occurs, the setup request has to be ack?ed and the stallrq request and stalli sent flags are automatically reset (rxsetupi set, txini cleared, stalli cleared, txini cleared...). this management simplifies the enumeration process management. if a command is not supported or contains an error, the firmware set the stall request flag and can return to the main task, waiting for the next setup request. en=1 d + uvref d - detach, then attach en=1 d + uvref d -
106 AT85C51SND3bx 7632a?mp3?03/06 this function is compliant with the chapter 8 test from pmtc that send extra status for a get_descriptor. the firmware sets the stall request just after receiving the sta - tus. all extra status will be automatically stall?ed until the next setup request. stall handshake and retry mechanism the retry mechanism has priority over the stall handshake. a stall handshake is sent if the stallrq request bit is set and if there is no retry required. control endpoint management a setup request is always ack?ed. when a new setup packet is received, the rxstpi interrupt is triggered (if enabled). the rxouti interrupt is not triggered. the fifocon and rwal fields are irrelevant with control endpoints. the firmware shall thus never use them on that endpoints. when read, their value is always 0. control endpoints are managed by the following bits: ? rxstpi is set when a new setup is received. it shall be cleared by firmware to acknowledge the packet and to clear the endpoint bank . ? rxouti is set when a new out data is received. it shall be cleared by firmware to acknowledge the packet and to clear the endpoint bank . ? txini is set when the bank is ready to accept a new in packet. it shall be cleared by firmware to send the packet and to clear the endpoint bank . control endpoints should not be managed by interrupts, but only by polling the sta - tus bits. control write the next figure shows a control write transaction. during the status stage, the controller will not necessary send a nak at the first in token: ? if the firmware knows the exact number of descriptor bytes that must be read, it can then anticipate on the status stage and send a zlp for the next in token, ? or it can read the bytes and poll nakini, which tells that all the bytes have been sent by the host, and the transaction is now in the status stage. setup rxstpi rxouti txini usb line hw sw out hw sw out hw sw in in nak sw data setup status
107 AT85C51SND3bx 7632a?mp3?03/06 control read the next figure shows a control read transaction. the usb controller has to manage the simultaneous write requests from the cpu and the usb host: a nak handshake is always generated at the first status stage command. when the controller detect the status stage, all the data written by the cpu are erased, and clearing txini has no effects. the firmware checks if the transmission is complete or if the reception is complete. the out retry is always ack?ed. this reception: - set the rxouti flag (received out data) - set the txini flag (data sent, ready to accept new data) software algorithm: set transmit ready wait (transmit complete or receive complete) if receive complete, clear flag and return if transmit complete, continue once the out status stage has been received, the usb controller waits for a setup request. the setup request have priority over any other request and has to be ack?ed. this means that any other flag should be cleared and the fifo reset when a setup is received. warning: the byte counter is reset when the out zero length packet is received. the firmware has to take care of this. out endpoint management out packets are sent by the host. all the data can be read by the cpu, which acknowl - edges or not the bank when it is empty. overview the endpoint must be configured first. ?manual? mode each time the current bank is full, the rxouti and the fifocon bits are set. this trig - gers an interrupt if the rxoute bit is set. the firmware can acknowledge the usb interrupt by clearing the rxouti bit. the firmware read the data and clear the fifo - con bit in order to free the current bank. if the out endpoint is composed of multiple setup rxstpi rxouti txini usb line hw sw in hw sw in out out nak sw sw hw wr enable host wr enable cpu data setup status
108 AT85C51SND3bx 7632a?mp3?03/06 banks, clearing the fifocon bit will switch to the next bank. the rxouti and fifo - con bits are then updated by hardware in accordance with the status of the new bank. rxouti shall always be cleared before clearing fifocon. the rwal bit always reflects the state of the current bank. this bit is set if the firmware can read data from the bank, and cleared by hardware when the bank is empty. ?autoswitch? mode in this mode, the clear of the fifocon bit is performed automatically by hardware each time the endpoint bank is empty. the firmware has to check if the next bank is empty or not before reading the next data. on rxouti interrupt, the firmware reads a complete bank. a new interrupt will be gener ated each time the current bank contains data to read. the acknowledge of the rxouti interrupt is always performed by software. detailed description standard mode without autosw in this mode (autosw cleared), the data are read by the cpu, following the next flow: ? when the bank is filled by the host, an endpoint interrupt (epintx) is triggered, if enabled (rxoute set) and rxouti is set. the cpu can also poll rxouti or fifocon, depending on the software architecture, ? the cpu acknowledges the interrupt by clearing rxouti, ? the cpu can read the number of byte (n) in the current bank (n=byct), out data (to bank 0) ack rxouti fifocon hw out data (to bank 0) ack hw sw sw sw example with 1 out data bank read data from cpu bank 0 out data (to bank 0) ack rxouti fifocon hw out data (to bank 1) ack sw sw example with 2 out data banks read data from cpu bank 0 hw sw read data from cpu bank 0 read data from cpu bank 1 nak
109 AT85C51SND3bx 7632a?mp3?03/06 ? the cpu can read the data from the current bank (?n? read of uedatx), ? the cpu can free the bank by clearing fifocon when all the data is read, that is: ? after ?n? read of uedatx, ? as soon as rwal is cleared by hardware. if the endpoint uses 2 banks, the second one can be filled by the host while the current one is being read by the cpu. then, when the cpu clear fifocon, the next bank may be already ready and rxouti is set immediately. standard mode with autosw in this mode (autosw set), the flow operation is the same as section ?standard mode without autosw?, page 108 , with the exception that the cpu does not have to free the bank (fifocon cleared): this will automatically be done when the cpu read the last byte of the bank. ? epintx (rxoute set, rxouti set) or polling on rxouti=1 or fifocon=1, ? the cpu acknowledges the interrupt by clearing rxouti, ? the cpu read the number of byte (n) in the current bank (n=byct) (or already knows the number ?n? of bytes at each packet), ? the cpu can read the data from the current bank (?n? read of uedatx, or can read while rwal is set). a clear of fifocon does not have any effects in this mode. using the dfc with autosw in this mode (autosw set, dfc programmed), the data are handled by the dfc with - out any intervention from the cpu. the flow is: ? programming of the dfc, ? poll end of transfer from the dfc. the bank switching is automatically done: when a bank is emptied, it is freed and the switch occurs. if the end of transfer occurs while the bank is not emptied, the cpu has the responsibility to free it. the cpu shall not use uedatx or the byte counter byct in this mode. a clear of fifocon does not have any effects in this mode. if a zlp is received, it will be filtered by the usb device controller, and the flag zlp - seen is set. using the dfc without autosw in this mode (autosw cleared, dfc programmed), the data are handled by the dfc but the cpu have to acknowledge each bank read. ? programming of the dfc, ? epintx (rxoute set, rxouti set) or polling on rxouti=1 or fifocon=1, ? the cpu acknowledges the interrupt by clearing rxouti, ? poll the wait of the transfer: (while rwal is set: wait), ? clear fifocon which frees the bank and switch to the next one. in endpoint management in packets are sent by the usb device controller, upon an in request from the host. all the data can be written by the cpu, which acknowledge or not the bank when it is full. overview the endpoint must be configured first. ?manual? mode the txini bit is set by hardware when the current bank becomes free. this triggers an interrupt if the txine bit is set. the fifocon bit is set at the same time. the cpu
110 AT85C51SND3bx 7632a?mp3?03/06 writes into the fifo and clears the fifocon bit to allow the usb controller to send the data. if the in endpoint is composed of multiple banks, this also switches to the next data bank. the txini and fifocon bits are automatically updated by hardware regarding the status of the next bank. txini shall always be cleared before clearing fifocon. the rwal bit always reflects the state of the current bank. this bit is set if the firmware can write data to the bank, and cleared by hardware when the bank is full. ?autoswitch? mode in this mode, the clear of the fifocon bit is performed automatically by hardware each time the endpoint bank is full. the firmware has to check if the next bank is empty or not before writing the next data. on txini interrupt, the firmware fills a complete bank. a new interrupt w ill be generat ed each time the current bank becomes free. detailed description standard mode without autosw in this mode (autosw cleared), the data are written by the cpu, following the next flow: ? when the bank is empty, an endpoint interrupt (epintx) is triggered, if enabled (txine set) and txini is set. the cpu can also poll txini or fifocon, depending the software architecture choice, ? the cpu acknowledges the interrupt by clearing txini, ? the cpu can write the data into the current bank (write in uedatx), in data (bank 0) ack txini fifocon hw example with 1 in data bank write data from cpu bank 0 example with 2 in data banks sw sw sw sw in in data (bank 0) ack txini fifocon write data from cpu bank 0 sw sw sw sw in data (bank 1) ack write data from cpu bank 0 write data from cpu bank 1 sw hw write data from cpu bank0 nak
111 AT85C51SND3bx 7632a?mp3?03/06 ? the cpu can free the bank by clearing fifocon when all the data are written, that is: ? after ?n? write into uedatx ? as soon as rwal is cleared by hardware. if the endpoint uses 2 banks, the second one can be read by the host while the current is being written by the cpu. then, when the cpu clears fifocon, the next bank may be already ready (free) and txini is set immediately. standard mode with autosw in this mode (autosw set), the flow operation is the same as section ?standard mode without autosw?, page 110 , with the exception that the cpu does not have to free the bank (fifocon cleared): this will automa tically be done when the cpu fills the bank. ? epintx (txine set, txini set) or polling on txini=1 or fifocon=1, ? the cpu acknowledges the interrupt by clearing txini, ? the cpu can write the data to the current bank (write in uedatx) while rwal is set. a clear of fifocon does not have any effects in this mode. using the dfc with autosw in this mode (autosw set, dfc programmed), the data are handled by the dfc with - out any intervention from the cpu. the flow is: ? programming of the dfc, ? poll end of transfer from the dfc. the bank switching is automatically done: when a bank is filled, it is freed and the switch occurs. if the end of transfer occurs while the bank is not filled, the cpu has the responsibility to free it. the cpu shall not use uedatx or the byte counter byct in this mode. a clear of fifocon does not have any effects in this mode. using the dfc without autosw in this mode (autosw=0, dfc programmed), the data are handled by the dfc but the cpu have to acknowledge each bank written: ? programming of the dfc, ? epintx (txine set, txini set) or polling on txini=1 or fifocon=1, ? the cpu acknowledges the interrupt by clearing txini, ? poll the wait of the transfer: (while rwal is set: wait), ? clear fifocon which frees the bank and switch to the next one. abort an ?abort? stage can be produced by the host in some situations: ? in a control transaction: zlp data out received during a in stage, ? in an isochronous in transaction: zlp data out received on the out endpoint during a in stage on the in endpoint ?? the killbk bit is used to kill the last ?written? bank. the best way to manage this abort is to perform the following operations:
112 AT85C51SND3bx 7632a?mp3?03/06 table 111. abort flow isochronous mode for isochronous in endpoints, it is possible to automatically switch the banks on each start of frame (sof). this is done by settin g isosw. the cpu has to fill the ban k of the endpoint; the bank switching w ill be automatic as soon as a sof is seen by the hardware. a clear of fifocon does not have any effects in this mode. in the case that a sof is missing (noise on usb pad, ?), the controller will automati - cally build internally a ?pseudo? start of frame and the bank switching is made. the sofi interrupt is triggered and the frame number fnum10:0 is increased. underflow an underflow can occur during in stage if the host attempts to read a bank which is empty. in this situation, the underfi interrupt is triggered. an underflow can also occur during out stage if the host send a packet while the banks are already full. typically, he cpu is not fast enough. the packet is lost. it is not possible to have underflow error during out stage, in the cpu side, since the cpu should read only if the bank is ready to give data (rxouti=1 or rwal=1) crc error a crc error can occur during out stage if the usb controller detects a bad received packet. in this situation, the stalli interrupt is triggered. this does not prevent the rxouti interrupt from being triggered. overflow in control, isochronous, bulk or interrupt endpoint, an overflow can occur during out stage, if the host attempts to write in a bank that is too small for the packet. in this situa - tion, the overfi interrupt is triggered (if enabled). the packet is acknowledged and the rxouti interrupt is also triggered (if enabled). the bank is filled with the first bytes of the packet. it is not possible to have overflow error during in stage, in the cpu side, since the cpu should write only if the bank is ready to access data (txini=1 or rwal=1). endpoint abort abort done abort is based on the fact that no banks are busy, meaning that nothing has to be sent. disable the txini interrupt. endpoint reset nbusybk =0 yes clear ueienx. txine no killbk=1 killbk=1 yes kill the last written bank. wait for the end of the procedure. no
113 AT85C51SND3bx 7632a?mp3?03/06 interrupts figure 62 shows all the device interrupts sources while figure 63 details the endpoint interrupt sources. figure 62. usb device controller interrupt system there are 2 kinds of interrupts: processing (i.e. their generation are part of the normal processing) and exception (errors). processing interrupts are generated when the following events are triggered: ? vbusti: vbus plug-in detection (insert, remove) ? uprsmi: upstream resume ? eorsmi: end of resume ? wakeupi: wake up ? eorsti: end of reset (speed initialization) ? sofi: start of frame (fncerr= 0) ? msofi: micro start of frame (fncerr= 0) ? suspi: suspend detected after 3 ms of inactivity exception interrupts are generated when the following events are triggered: ? sofi: crc error in frame number of sof (fncerr= 1) ? msofi: crc error in frame number of micro-sof (fncerr= 1) eorsmi udint.5 eorsme udien.5 msofi udint.1 msofe udien.1 sofi udint.2 sofe udien.2 wakeupi udint.4 wakeupe udien.4 uprsmi udint.6 uprsme udien.6 suspi udint.0 suspe udien.0 eorsti udint.3 eorste udien.3 usb device interrupt
114 AT85C51SND3bx 7632a?mp3?03/06 figure 63. usb device controller endpoint interrupt system processing interrupts are generated when the following events are triggered: ? txini: ready to accept in data ? rxouti: out data received ? rxstpi: setup received exception interrupts are generated when the following events are triggered: ? stalli: stalled packet ? stalli: crc error on out in isochronous mode ? overfi: overflow in isochronous mode ? underfi: underflow in isochronous mode ? nakini: nak in sent ? nakouti: nak out sent flerre ueienx.7 rxouti ueintx.2 rxoute ueienx.2 rxstpi ueintx.3 rxstpe ueienx.3 nakini ueintx.6 nakine ueienx.6 overfi uesta0x.6 stalli ueintx.1 stalle ueienx.1 txini ueintx.0 txine ueienx.0 nakouti ueintx.4 nakoute ueienx.4 endpoint s interrupt epintn ueint.n underfi uesta0x.5 endpoint n (n= 0-6)
115 AT85C51SND3bx 7632a?mp3?03/06 registers usb device general registers reset value = 0000 0001b table 112. udcon register udcon ( 1.d9h ) ? usb device general control register 7 6 5 4 3 2 1 0 - - - - - - rmwkup detach bit number bit mnemonic description 7-2 - reserved the value read from these bits is always 0. do not set these bits. 1 rmwkup remote wake-up bit set to send an ?upstream-resume? to the host for a remote wake-up. cleared by hardware. clearing by software has no effect. see section ?remote wake-up? for more details. 0 detach detach bit set to physically detach de device. clear to reconnect the device. see section ?detach? for more details. table 113. udint register udint ( 1.d8h ) ? usb device global interrupt register 7 6 5 4 3 2 1 0 - uprsmi eorsmi wakeupi eorsti sofi msofi suspi bit number bit mnemonic description 7 - reserved the value read from these bits is always 0. do not set these bits. 6 uprsmi upstream resume interrupt flag set by hardware when the usb controller is sending a resume signal called ?upstream resume?. this triggers an usb interrupt if uprsme is set. shall be cleared by software (usb clocks must be enabled before). setting by software has no effect. 5 eorsmi end of resume interrupt flag set by hardware when the usb controller detects a good ?end of resume? signal initiated by the host. this triggers an usb interrupt if eorsme is set. shall be cleared by software. setting by software has no effect. 4 wakeupi wake-up cpu interrupt flag set by hardware when the usb controller is re-activated by a filtered non-idle signal from the lines (not by an upstream resume). this triggers an interrupt if wakeupe is set. shall be cleared by software (usb clock inputs must be enabled before). setting by software has no effect. see section ?suspend, wake-up and resume? for more details.
116 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b 3 eorsti end of reset interrupt flag set by hardware when an ?end of reset? has been detected by the usb controller. this triggers an usb interrupt if eorste is set. shall be cleared by software. setting by software has no effect. 2 sofi start of frame interrupt flag set by hardware when an usb ?start of frame? pid (sof) has been detected (every 1 ms). this triggers an usb interrupt if sofe is set. 1 msofi micro-start of frame interrupt flag set by hardware when an usb ?micro-start of frame? pid (sof) has been detected (every 125 s). this triggers an usb interrupt if msofe is set. 0 suspi suspend interrupt flag set by hardware when an usb ?suspend? ?idle bus for 3 frame periods: a j state for 3 ms) is detected. this triggers an usb interrupt if suspe is set. shall be cleared by software. setting by software has no effect. see section ?suspend, wake-up and resume? for more details. table 114. udien register udien ( 1.dah ) ? usb device global interrupt enable register 7 6 5 4 3 2 1 0 - uprsme eorsme wakeupe eorste sofe msofe suspe bit number bit mnemonic description 7 - reserved the value read from these bits is always 0. do not set these bits. 6 uprsme upstream resume interrupt enable bit set to enable the uprsmi interrupt. clear to disable the uprsmi interrupt. 5 eorsme end of resume interrupt enable bit set to enable the eorsmi interrupt. clear to disable the eorsmi interrupt. 4 wakeupe wake-up cpu interrupt enable bit set to enable the wakeupi interrupt. clear to disable the wakeupi interrupt. 3 eorste end of reset interrupt enable bit set to enable the eorsti interrupt. this bit is set after a reset. clear to disable the eorsti interrupt. 2 sofe start of frame interrupt enable bit set to enable the sofi interrupt. clear to disable the sofi interrupt. 1 msofe micro-start of frame interrupt enable bit set to enable the msofi interrupt. clear to disable the msofi interrupt. bit number bit mnemonic description
117 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b 0 suspe suspend interrupt enable bit set to enable the suspi interrupt. clear to disable the suspi interrupt. table 115. udaddr register udaddr ( 1.dbh ) ? usb device address register 7 6 5 4 3 2 1 0 adden uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 bit number bit mnemonic description 7 adden address enable bit set to activate the uadd (usb address). cleared by hardware. clearing by software has no effect. see section ?address setup? for more details. 6-0 uadd6:0 usb address bits set to configure the device address. shall not be cleared. table 116. udfnumh register udfnumh ( 1.dch ) ? usb device frame number high register 7 6 5 4 3 2 1 0 - - - - - fnum10 fnum9 fnum8 bit number bit mnemonic description 7-3 - reserved the value read from these bits is always 0. do not set these bits. 2-0 fnum10:8 frame number upper flag set by hardware. these bits are the 3 msb of the 11-bits frame number information. they are provided in the last received sof packet. fnum is updated if a corrupted sof is received. table 117. udfnuml register udfnuml ( 1.ddh ) ? usb device frame number low register 7 6 5 4 3 2 1 0 fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 bit number bit mnemonic description
118 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b usb device endpoint registers reset value = 0000 0000b bit number bit mnemonic description 7-0 fnum7:0 frame number lower flag set by hardware. these bits are the 8 lsb of the 11-bits frame number information. table 118. udmfn register udmfn ( 1.deh ) ? usb device frame number register 7 6 5 4 3 2 1 0 - - - fncerr - - - - bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4 fncerr frame number crc error flag set by hardware when a corrupted frame number in start of frame packet is received. this bit and the sofi interrupt are updated at the same time. 3-0 - reserved the value read from these bits is always 0. do not set these bits. table 119. uenum register uenum ( 1.c9h ) ? usb endpoint number selection register 7 6 5 4 3 2 1 0 - - - - - epnum2 epnum1 epnum0 bit number bit mnemonic description 7-3 - reserved the value read from these bits is always 0. do not set these bits. 2-0 epnum2:0 endpoint number bits set to select the number of the endpoint which shall be accessed by the cpu. see section ?endpoint selection? for more details. epnum = 111b is forbidden. table 120. uerst register uerst ( 1.cah ) ? usb endpoint reset register 7 6 5 4 3 2 1 0 - eprst6 eprst5 eprst4 eprst3 eprst2 eprst1 eprst0
119 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b bit number bit mnemonic description 7 - reserved the value read from these bits is always 0. do not set these bits. 6-0 eprst6:0 endpoint fifo reset bits set to reset the selected endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. see section ?endpoint reset? for more information. then, cleared by software to complete the reset operation and start using the fifo. table 121. ueconx register ueconx ( 1.cbh ) ? usb endpoint control register 7 6 5 4 3 2 1 0 - - stallrq stallrqc rstdt epnums dfcrdy epen bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 stallrq stall request handshake bit set to request a stall answer to the host for the next handshake. cleared by hardware when a new setup is received. clearing by software has no effect. see section ?stall request? for more details. 4 stallrqc stall request clear handshake bit set to disable the stall handshake mechanism. cleared by hardware immediately after the set. clearing by software has no effect. see section ?stall request? for more details. 3 rstdt reset data toggle bit set to automatically clear the data toggle sequence: for out endpoint: the next received packet will have the data toggle 0. for in endpoint: the next packet to be sent will have the data toggle 0. cleared by hardware instantaneously. the firmware does not have to wait that the bit is cleared. clearing by software has no effect. 2 epnums endpoint number select bit set to configure the epnum used by the dfc. clear to select the epnum used by the cpu. 1 dfcrdy dfc ready bit set to resume/enable the dfc interface. clear to pause the dfc interface. 0 epen endpoint enable bit set to enable the endpoint according to the device configuration. endpoint 0 shall always be enabled after a hardware or usb reset and participate in the device configuration. clear this bit to disable the endpoint. see section ?endpoint activation? for more details.
120 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 122. uecfg0x register uecfg0x ( 1.cch ) ? usb endpoint configuration 1 register 7 6 5 4 3 2 1 0 eptype1:0 - - isosw autosw nyetdis epdir bit number bit mnemonic description 7-6 eptype1:0 endpoint type bits set this bit according to the endpoint configuration: 00b: control10b: bulk 01b: isochronous11b: interrupt 5-4 - reserved the value read from these bits is always 0. do not set these bits. 3 isosw isochronous switch bit set to automatically switch banks on each sof. clear to disable the automatic bank switching on each sof. see section ?isochronous mode? for more details. 2 autosw automatic switch bit set to automatically switch bank when it is ready. clear to disable the automatic bank switching. see section ?out endpoint management? and section ?in endpoint management? for more details. 1 nyetdis not yet disable bit set to automatically send a ?ack? handshake instead of ?not yet? handshake. thus, the host will not have to ?ping? for the next packet. clear to automatically send ?not yet? handshake. thus, the host will have to ?ping? for the next packet. 0 epdir endpoint direction bit set to configure an in direction for bulk, interrupt or isochronous endpoints. clear to configure an out direction for bulk, interrupt, isochronous or control endpoints. table 123. uecfg1x register uecfg1x ( 1.cdh ) ? usb endpoint configuration 0 register 7 6 5 4 3 2 1 0 - epsize2 epsize1 epsize0 epbk1 epbk alloc - bit number bit mnemonic description 7 - reserved the value read from these bits is always 0. do not set these bits. 6-4 epsize2:0 endpoint size bits set this bit according to the endpoint size: 000b: 8 bytes100b: 128 bytes 001b: 16 bytes101b: 256 bytes 010b: 32 bytes110b: 512 bytes 011b: 64 bytes111b: reserved. do not use this configuration.
121 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b 3-2 epbk1:0 endpoint bank bits set this field according to the endpoint size: 00b: single bank 01b: double bank 1xb: reserved. do not use this configuration. 1 alloc endpoint allocation bit set this bit to allocate the endpoint memory. clear to free the endpoint memory. see section ?endpoint activation? for more details. 0 - reserved the value read from these bits is always 0. do not set these bits. table 124. uesta0x register uesta0x ( 1.ceh ) ? usb endpoint status 0 register 7 6 5 4 3 2 1 0 cfgok overfi underfi zlpseen dtseq1 dtseq0 nbusybk1 nbusybk0 bit number bit mnemonic description 7 cfgok configuration status flag set by hardware when the endpoint x size parameter (epsize) and the bank parametrization (epbk) are correct compared to the max fifo capacity and the max number of allowed bank. this bit is updated when the bit alloc is set. if this bit is cleared, the user should reprogram the uecfg1x register with correct epsize and epbk values. 6 overfi overflow error interrupt flag set by hardware when an overflow error occurs in an isochronous endpoint. an interrupt (epintx) is triggered (if enabled). see section ?isochronous mode? for more details. shall be cleared by software. setting by software has no effect. 5 underfi flow error interrupt flag set by hardware when an underflow error occurs in an isochronous endpoint. an interrupt (epintx) is triggered (if enabled). see section ?isochronous mode? for more details. shall be cleared by software. setting by software has no effect. 4 zlpseen zero length packet seen (bit / flag) set by hardware, as soon as a zlp has been filtered during a transfer. shall be cleared by the software. setting by software has no effect. 3-2 dtseq1:0 data toggle sequencing flag set by hardware to indicate the pid data of the current bank: 00b: data0 01b: data1 1xb: reserved. for out transfer, this value indicates the last data toggle received on the current bank. for in transfer, it indicates the toggle that will be used for the next packet to be sent. this is not relative to the current bank. bit number bit mnemonic description
122 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b 1-0 nbusybk1: 0 busy bank flag set by hardware to indicate the number of busy bank. for in endpoint, it indicates the number of busy bank(s), filled by the user, ready for in transfer. for out endpoint, it indicates the number of busy bank(s) filled by out transaction from the host. 00b: all banks are free 01b: 1 busy bank 10b: 2 busy banks 11b: reserved. table 125. uesta1x register uesta1x ( 1.cfh ) ? usb endpoint status 1 register 7 6 5 4 3 2 1 0 - - - - - ctrldir currbk1 currbk0 bit number bit mnemonic description 7-3 - reserved the value read from these bits is always 0. do not set these bits. 2 ctrldir control direction (flag, and bit for debug purpose) set by hardware after a setup packet, and gives the direction of the following packet: - 1 for in endpoint - 0 for out endpoint. can not be set or cleared by software. 1-0 currbk1:0 current bank (all endpoints except control endpoint) flag set by hardware to indicate the number of the current bank: 00b: bank0 01b: bank1 1xb: reserved. can not be set or cleared by software. bit number bit mnemonic description
123 AT85C51SND3bx 7632a?mp3?03/06 table 126. ueintx register (bit addressable) ueintx ( 1.c8h ) ? usb endpoint interrupt register 7 6 5 4 3 2 1 0 fifocon nakini rwal nakouti rxstpi rxouti stalli txini bit number bit mnemonic description 7 fifocon fifo control bit for out and setup endpoint: set by hardware when a new out message is stored in the current bank, at the same time than rxout or rxstp. clear to free the current bank and to switch to the following bank. setting by software has no effect. for in endpoint: set by hardware when the current bank is free, at the same time than txin. clear to send the fifo data and to switch the bank. setting by software has no effect. 6 nakini nak in received interrupt flag set by hardware when a nak handshake has been sent in response of a in request from the host. this triggers an usb interrupt if nakine is sent. shall be cleared by software. setting by software has no effect. 5 rwal read/write allowed flag set by hardware to signal: - for an in endpoint: the current bank is not full i.e. the firmware can push data into the fifo, - for an out endpoint: the current bank is not empty, i.e. the firmware can read data from the fifo. the bit is never set if stallrq is set, or in case of error. cleared by hardware otherwise. this bit shall not be used for the control endpoint. 4 nakouti nak out received interrupt flag set by hardware when a nak handshake has been sent in response of a out/ping request from the host. this triggers an usb interrupt if nakoute is sent. shall be cleared by software. setting by software has no effect. 3 rxstpi received setup interrupt flag set by hardware to signal that the current bank contains a new valid setup packet. an interrupt (epintx) is triggered (if enabled). shall be cleared by software to handshake the interrupt. setting by software has no effect. this bit is inactive (cleared) if the endpoint is an in endpoint. 2 rxouti / killbk received out data interrupt flag set by hardware to signal that the current bank contains a new packet. an interrupt (epintx) is triggered (if enabled). shall be cleared by software to handshake the interrupt. setting by software has no effect. kill bank in bit set this bit to kill the last written bank. cleared by hardware when the bank is killed. clearing by software has no effect. see section ?abort? for more details on the abort.
124 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b 1 stalli stall interrupt flag set by hardware to signal that a stall handshake has been sent, or that a crc error has been detected in a out isochronous endpoint. shall be cleared by software. setting by software has no effect. 0 txini transmitter ready interrupt flag set by hardware to signal that the current bank is free and can be filled. an interrupt (epintx) is triggered (if enabled). shall be cleared by software to handshake the interrupt. setting by software has no effect. this bit is inactive (cleared) if the endpoint is an out endpoint. table 127. ueienx register ueienx ( 1.d2h ) ? usb endpoint interrupt enable register 7 6 5 4 3 2 1 0 flerre nakine - nakoute rxstpe rxoute stalle txine bit number bit mnemonic description 7 flerre flow error interrupt enable flag set to enable an endpoint interrupt (epintx) when overfi or underfi are sent. clear to disable an endpoint interrupt (epintx) when overfi or underfi are sent. 6 nakine nak in interrupt enable bit set to enable an endpoint interrupt (epintx) when nakini is set. clear to disable an endpoint interrupt (epintx) when nakini is set. 5 - reserved the value read from these bits is always 0. do not set these bits. 4 nakoute nak out interrupt enable bit set to enable an endpoint interrupt (epintx) when nakouti is set. clear to disable an endpoint interrupt (epintx) when nakouti is set. 3 rxstpe received setup interrupt enable flag set to enable an endpoint interrupt (epintx) when rxstpi is sent. clear to disable an endpoint interrupt (epintx) when rxstpi is sent. 2 rxoute received out data interrupt enable flag set to enable an endpoint interrupt (epintx) when rxouti is sent. clear to disable an endpoint interrupt (epintx) when rxouti is sent. 1 stalle stall interrupt enable flag set to enable an endpoint interrupt (epintx) when stalli is sent. clear to disable an endpoint interrupt (epintx) when stalli is sent. 0 txine transmitter ready interrupt enable flag set to enable an endpoint interrupt (epintx) when txini is sent. clear to disable an endpoint interrupt (epintx) when txini is sent. bit number bit mnemonic description
125 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b table 128. uedatx register uedatx ( 1.d3h ) ? usb endpoint data register 7 6 5 4 3 2 1 0 dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 bit number bit mnemonic description 7-0 dat7:0 data bits set by the software to read/write a byte from/to the endpoint fifo selected by epnum. table 129. uebchx register uebchx ( 1.d4h ) ? usb endpoint byte counter high register 7 6 5 4 3 2 1 0 - - - - - byct10 byct9 byct8 bit number bit mnemonic description 7-3 - reserved the value read from these bits is always 0. do not set these bits. 2-0 byct10:8 byte count (high) bits set by hardware. this field is the msb of the byte count of the fifo endpoint. the lsb part is provided by the uebclx register. table 130. uebclx register uebclx ( 1.d5h ) ? usb endpoint byte counter low register 7 6 5 4 3 2 1 0 byct7 byct6 byct5 byct4 byct3 byct2 byct1 byct0 bit number bit mnemonic description 7-0 byct7:0 byte count (low) bits set by the hardware. byct10:0 is: - (for in endpoint) increased after each writing into the endpoint and decremented after each byte sent, - (for out endpoint) increased after each byte sent by the host, and decremented after each byte read by the software.
126 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b. table 131. ueint register ueint ( 1.d6h ) ? usb endpoint interrupt register 7 6 5 4 3 2 1 0 - epint6 epint5 epint4 epint3 epint2 epint1 epint0 bit number bit mnemonic description 7 - reserved the value read from these bits is always 0. do not set these bits. 6-0 epint6:0 endpoint interrupts bits set by hardware when an interrupt is triggered by the ueintx register and if the corresponding endpoint interrupt enable bit is set. cleared by hardware when the interrupt source is served.
127 AT85C51SND3bx 7632a?mp3?03/06 usb host operating modes pipe description for the usb host controller, the term of pipe is used instead of endpoint for the usb device controller (see figure 64 ). a host pipe corresponds to a device endpoint, as described in the usb specification. figure 64. pipes and endpoints in a usb system in the usb host controller, a pipe will be associated to a device endpoint, considering the device configuration descriptors. detach the reset value of the detach bit is 1. thus, the firmware has the responsibility of clearing this bit before switching to the host mode (host set). power-on and reset figure 65 shows the usb host controller main states after power-on. figure 65. usb host controller reset state machine usb host controller state after an hardware reset is ?reset?. when the usb controller is enabled and the usb host controller is selected, the usb controller is in ?idle? state. in this state, the usb host controller waits for the device connection, with a minimum power consumption . the usb pad should be in idle mode. the macro does not need to have the pll activated to enter in ?host ready? state. host ready host idle device disconnection device connection clock stopped macro off device disconnection host suspend sofe=1 sofe=0
128 AT85C51SND3bx 7632a?mp3?03/06 the host controller enters in suspend state when the usb bus is in suspend state, i.e. when the host controller doesn?t generate the start of frame. in this state, the usb con - sumption is minimum. the host controller exits to the suspend state when starting to generate the sof over the usb line. device detection a device is detected by the usb controller when the usb bus if different from d+ and d- low. in other words, when the usb host controller detects the device pull-up on the d+ line. to enable this detection, the host controller has to provide the vbus power supply to the device. the device disconnection is detected by the usb host controller when the usb idle correspond to d+ and d- low on the usb line. pipe selection prior to any operation performed by the cpu, the pipe must first be selected. this is done by: ? clearing pnums. ? setting pnum with the pipe number which will be managed by the cpu. the cpu can then access to the various pipe registers and data. in the same manner, if the pipe must be accessed by the dfc, it must first be selected. this is done by: ? setting pnums. ? setting pnum with the pipe number which will be managed by the dfc. ? setting dfcrdy when the data-flow is ready to take place. the dfc can then access to the banks (read / write). the controller internally keeps in memory the pnum for the cpu and the pnum for the dfc. in fact, there are 2 pnum registers multiplexed by the pnums bit. each of them can be read or written by the cpu. these two registers permits to easily switch from a pipe under dfc data transfer to the default control pipe when a setup has to be sent, without reprogramming the epnum register: ?set pnums, ?pnum = pipe x ? set dfcrdy when the dfc transfer is ready to take place, ? ...... ? setup required on pipe 0 , ? clear dfcrdy to freeze the dfc transfer, ? pnums cleared, ?pnum = pipe 0 ? manage pipe 0 data ? set dfcrdy. this resumes the dfc transfer.
129 AT85C51SND3bx 7632a?mp3?03/06 pipe configuration the following flow must be respected in order to activate a pipe: figure 66. pipe activation flow: once the pipe is activated (epen set) and, the hardware is ready to send requests to the device. when configured (cfgok = 1), only the pipe token (ptoken) and the polling interval for interrupt pipe can be modified. a control type pipe supports only 1 bank. any other value will lead to a configuration error (cfgok = 0). a clear of pen will reset the configuration of the pipe. all the corresponding pipe regis - ters are reset to there reset values. please refers to the memory management chapter for more details. note: the firmware has to configure the default control pipe with the following parameters: ? type: control ? token: setup ? data bank: 1 ? size: 64 bytes the firmware asks for 8 bytes of the device descriptor sending a get_descriptor request. these bytes contains the maxpacketsize of the device default control endpoint and the firmware re-configures the size of the default control pipe with this size parameter. pipe activ ation upconx penable=1 upcfg0x ptype ptoken pepnum cfgok=1 error no yes upcfg2x intfrq (interrupt only) pipe activ ated and f reezed upcfg1x psize pbk cfgmem enable the pipe select the pipe type: * type (control, bulk, interrup t) * token (in, out , setup) * endpoint number configure the pipe memory: * pipe size * number of banks confi gure the polling interval for interrupt pipe
130 AT85C51SND3bx 7632a?mp3?03/06 usb reset the usb controller sends a usb reset when the firmware set the r eset bit. the rsti bit is set by hardware when the usb reset has been sent. this triggers an interrupt if the rste has been set. when a usb reset has been sent, all the pipe configuration and the memory allocation are reset. the general host interrupt enable register is left unchanged. if the bus was previously in suspend mode (sofe = 0), the usb controller automatically switches to the resume mode (hwupi is set) and the sofe bit is set by hardware in order to generate sof immediately after the usb reset. address setup once the device has answer to the first host requests with the default address (0), the host assigns a new address to the device. the host controller has to send a usb reset to the device and perform a set address control request, with the new address to be used by the device. this control request ended, the firmware write the new address into the uhaddr register. all following requests, on every pipes, will be performed using this new address. when the host controller send a usb reset, the uhaddr register is reset by hardware and the following host requests will be performed using the default address (0). remote wake-up detection the host controller enters in suspend mode when clearing the sofe bit. no more start of frame is sent on the usb bus and the usb device enters in suspend mode 3ms later. the device awakes the host controller by sending an upstream resume (remote wake-up feature). the host controller detects a non-idle state on the usb bus and set the hwupi bit. if the non-idle correspond to an upstream resume (k state), the rxrsmi bit is set by hardware. the firmware has to generate a downstream resume within 1ms and for at least 20ms by setting the resume bit. once the downstream resume has been generated, the sofe bit is automatically set by hardware in order to generate so f immediately after the usb resume. usb pipe reset the firmware can reset a pipe using the pipe reset register. the configuration of the pipe and the data toggle remains unchanged. only the bank management and the sta - tus bits are reset to their initial values. to completely reset a pipe, the firmware has to disable and then enable the pipe. pipe data access in order to read or to write into the pipe fifo, the cpu selects the pipe number with the upnum register and performs read or write action on the updatx register. control pipe management a control transaction is composed of 3 phases: ?setup ? data (in or out) ? status (out or in) host ready host suspend sofe=1 or hwup=1 sofe=0
131 AT85C51SND3bx 7632a?mp3?03/06 the firmware has to change the token for each phase. the initial data toggle is set for the corresponding token (only for control pipe): ? setup: data0 ? out: data1 ? in: data1 (expected data toggle) out pipe management the pipe must be configured and not frozen first. note: if the firmware decides to switch to suspend mode (clear sofe) even if a bank is ready to be sent, the usb controller will automatically exit from suspend mode and the bank will be sent.
132 AT85C51SND3bx 7632a?mp3?03/06 ?manual? mode the txout bit is set by hardware when the current bank becomes free. this triggers an interrupt if the txoute bit is set. the fifocon bit is set at the same time. the cpu writes into the fifo and clears the fifocon bit to allow the usb controller to send the data. if the out pipe is composed of multiple banks, this also switches to the next data bank. the txout and fifocon bits are automatically updated by hardware regarding the status of the next bank. out data (bank 0) ack txout fifocon hw example with 1 out data bank write data from cpu bank 0 example with 2 out data banks sw sw sw sw out out data (bank 0) ack txout fifocon write data from cpu bank 0 sw sw sw sw out data (bank 1) ack write data from cpu bank 0 write data from cpu bank 1 sw hw write data from cpu bank0 example with 2 out data banks out data (bank 0) ack txout fifocon write data from cpu bank 0 sw sw sw sw write data from cpu bank 1 sw hw write data from cpu bank0 out data (bank 1) ack
133 AT85C51SND3bx 7632a?mp3?03/06 ?autoswitch? mode in this mode, the clear of the fifocon bit is performed automatically by hardware each time the pipe bank is full. the firmware has to check if the next bank is empty or not before writing the next data. on txout interrupt, the firmware fills a complete bank. a new interrupt w ill be generat ed each time the current bank becomes free. in pipe management the pipe must be configured first. ?manual? mode when the host requires data from the device, the firmware has to determine first the in mode to use using the inmode bit: ? inmode = 0. the inrqx register is taken in account. the host controller will perform (inrqx+1) in requests on the selected pipe before freezing the pipe. this mode avoids to have extra in requests on a pipe. ? inmode = 1. the usb controller will perform infinite in request until the firmware freezes the pipe. the in request generation w ill start when the firmware clear the pfreeze bit. each time the current bank is full, the rxin and the fifocon bits are set. this triggers an interrupt if the rxine bit is set. the firmware can acknowledge the usb interrupt by clearing the rxin bit. the firmware read the data and clear the fifocon bit in order to free the current bank. if the in pipe is composed of multiple banks, clearing the fifo - con bit will switch to the next bank. the rxin and fifocon bits are then updated by hardware in accordance with the status of the new bank. in data (to bank 0) ack rxin fifocon hw in data (to bank 0) ack hw sw sw sw example with 1 in data bank read data from cpu bank 0 in data (to bank 0) ack rxin fifocon hw in data (to bank 1) ack sw sw example with 2 in data banks read data from cpu bank 0 hw sw read data from cpu bank 0 read data from cpu bank 1
134 AT85C51SND3bx 7632a?mp3?03/06 ?autoswitch? mode in this mode, the clear of the fifocon bit is performed automatically by hardware each time the pipe bank is empty. the firmware has to check if the next bank is empty or not before reading the next data. on rxin interrupt, the firmware reads a complete bank. a new interrupt will be generated each time the current bank contains data to read. the acknowledge of the rxin interrupt is always performed by software. crc error (isochronous only) a crc error can occur during in stage if the usb controller detects a bad received packet. in this situation, the stalledi/crcerri interrupt is triggered. this does not prevent the rxini interrupt from being triggered. interrupt figure 67 shows all the host interrupts sources while figure 68 details the pipe interrupt sources. figure 67. usb host controller interrupt system hsofi uhint.5 hsofe uhien.5 ddisci uhint.1 ddisce uhien.1 rsti uhint.2 rste uhien.2 rxrsmi uhint.4 rxrsme udien.4 hwupi uhint.6 hwupe uhien.6 dconni uhint.0 dconne uhien.0 rsmedi uhint.3 rsmede uhien.3 usb host interrupt
135 AT85C51SND3bx 7632a?mp3?03/06 figure 68. usb host controller pipe interrupt system flerre upienx.7 txouti upintx.2 txoute upienx.2 txstpi upintx.3 txstpe upienx.3 nakedi upintx.6 nakede upienx.6 overfi upstax.6 rxstalli upintx.1 rxstalle upienx.1 rxini upintx.0 rxine upienx.0 perri upintx.4 perre upienx.4 pipes interrupt pintn upint.n underfi uepstax.5 pipe n (n= 0-6)
136 AT85C51SND3bx 7632a?mp3?03/06 registers general usb host registers reset value = 0000 0000b table 132. uhcon register uhcon ( 1.d9h ) ? usb host general control register 7 6 5 4 3 2 1 0 - - - - - resume reset sofe bit number bit mnemonic description 7-3 - reserved the value read from these bits is always 0. do not set these bits. 2 resume send usb resume set this bit to generate a usb resume on the usb bus. cleared by hardware when the usb resume has been sent. clearing by software has no effect. 1 reset send usb reset set this bit to generate a usb reset on the usb bus. cleared by hardware when the usb reset has been sent. clearing by software has no effect. refer to the usb reset section for more details. 0 sofe start of frame generation enable set this bit to generate sof on the usb bus. clear this bit to disable the sof generation and to leave the usb bus in idle state. table 133. uhint register uhint (1.d8h) ? usb host general interrupt register 7 6 5 4 3 2 1 0 - hwup hsof rxrsmi rsmedi rsti ddisci dconni bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6 hwup host wake-up interrupt set by hardware when a non-idle state is detected on the usb bus. shall be clear by software to acknowledge the interrupt. setting by software has no effect. 5 hsofi host start of frame interrupt set by hardware when a sof is issued by the host controller. this triggers a usb interrupt when hsofe is set. shall be cleared by software to acknowledge the interrupt. setting by software has no effect.
137 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b 4 rxrsmi upstream resume received interrupt set by hardware when an upstream resume has been received from the device. shall be cleared by software. setting by software has no effect. 3 rsmedi downstream resume sent interrupt set by hardware when a downstream resume has been sent to the device. shall be cleared by software. setting by software has no effect. 2 rsti usb reset sent interrupt set by hardware when a usb reset has been sent to the device. shall be cleared by software. setting by software has no effect. 1 ddisci device disconnection interrupt set by hardware when the device has been removed from the usb bus. shall be cleared by software. setting by software has no effect. 0 dconni device connection interrupt set by hardware when a new device has been connected to the usb bus. shall be cleared by software. setting by software has no effect. table 134. uhien register uhien ( 1 . dah ) ? usb host general interrupt enable register 7 6 5 4 3 2 1 0 - hwupe hsofe rxrsme rsmede rste ddisce dconne bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6 hwupe host wake-up interrupt enable set this bit to enable hwup interrupt. clear this bit to disable hwup interrupt. 5 hsofe host start of frame interrupt enable set this bit to enable hsof interrupt. clear this bit to disable hsof interrupt. 4 rxrsme upstream resume received interrupt enable set this bit to enable the rxrsmi interrupt. clear this bit to disable the rxrsmi interrupt. 3 rsmede downstream resume sent interrupt enable set this bit to enable the rsmedi interrupt. clear this bit to disable the rsmedi interrupt. 2 rste usb reset sent interrupt enable set this bit to enable the rsti interrupt. clear this bit to disable the rsti interrupt. 1 ddisce device disconnection interrupt enable set this bit to enable the ddisci interrupt. clear this bit to disable the ddisci interrupt. bit number bit mnemonic description
138 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b 0 dconne device connection interrupt enable set this bit to enable the dconni interrupt. clear this bit to disable the dconni interrupt. table 135. uhaddr register uhaddr ( 1.dbh ) ? usb host address register 7 6 5 4 3 2 1 0 - haddr6 haddr5 haddr4 haddr3 haddr2 haddr1 haddr0 bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6-0 haddr6:0 usb host address these bits contains the address of the usb device. table 136. uhfnumh register uhfnumh ( 1.dch ) ? usb host frame number high register 7 6 5 4 3 2 1 0 - - - - - fnum10 fnum9 fnum8 bit number bit mnemonic description 7-4 - reserved the value read from these bits is always 0. do not set these bits. 3-0 fnum10:8 frame number the value contained in tis register is the current sof number. this value can be modified by software. bit number bit mnemonic description
139 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b usb host pipe registers reset value = 0000 0000b table 137. uhfnuml register uhfnuml ( 1.ddh ) ? usb host frame number low register 7 6 5 4 3 2 1 0 fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 bit number bit mnemonic description 7-0 fnum7:0 frame number the value contained in tis register is the current sof number. this value can be modified by software. table 138. uhflen register uhflen ( 1.deh ) ? usb host frame length register 7 6 5 4 3 2 1 0 flen7 flen6 flen5 flen4 flen3 flen2 flen1 flen0 bit number bit mnemonic description 7-0 flen7:0 frame length the value contained table 139. upnum register upnum ( 1.c9h ) ? usb host pipe number register 7 6 5 4 3 2 1 0 - - - - - pnum2 pnum1 pnum0 bit number bit mnemonic description 7-3 - reserved the value read from these bits is always 0. do not set these bits. 2-0 pnum2:0 pipe number select the pipe using this register. the usb host registers ended by a x correspond then to this number. this number is used for the usb controller following the value of the pnumd bit.
140 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 140. uprst register uprst ( 1.cah ) ? usb host pipe reset register 7 6 5 4 3 2 1 0 - p6rst p5rst p4rst p3rst p2rst p1rst p0rst bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6 p6rst pipe 6 reset set this bit to 1 and reset this bit to 0 to reset the pipe 6. 5 p5rst pipe 5 reset set this bit to 1 and reset this bit to 0 to reset the pipe 5. 4 p4rst pipe 4 reset set this bit to 1 and reset this bit to 0 to reset the pipe 4. 3 p3rst pipe 3 reset set this bit to 1 and reset this bit to 0 to reset the pipe 3. 2 p2rst pipe 2 reset set this bit to 1 and reset this bit to 0 to reset the pipe 2. 1 p1rst pipe 1 reset set this bit to 1 and reset this bit to 0 to reset the pipe 1. 0 p0rst pipe 0 reset set this bit to 1 and reset this bit to 0 to reset the pipe 0. table 141. upconx register upconx ( 1.cbh ) ? usb host pipe control register 7 6 5 4 3 2 1 0 - pfreeze inmode autosw rstdt pnum dfcrdy pen bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6 pfreeze pipe freeze set this bit to freeze the pipe requests generation. clear this bit to enable the pipe request generation. this bit is set by hardware when: - the pipe is not configured - a stall handshake has been received on this pipe - an error occurs on the pipe (perr = 1) - (inrq+1) in requests have been processed this bit is set at 1 by hardware after a pipe reset or a pipe enable.
141 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b 5 inmode in request mode set this bit to allow the usb controller to perform infinite in requests when the pipe is not frozen. clear this bit to perform a pre-defined number of in requests. this number is stored in the uinrqx register. 4 autosw auto switch bank set this bit to allow the auto switch bank mode for this pipe. clear this bit to otherwise. 3 rstdt reset data toggle set this bit to reset the data toggle to its initial value for the current pipe. cleared by hardware when proceed. clearing by software has no effect. 2 pnums pipe number select bit set to configure the pnum used by the dfc. clear to configure the pnum used by the cpu. 1 dfcrdy dfc ready bit set to resume/enable the dfc interface. clear to pause the dfc interface. 0 pen pipe enable set to enable the pipe. clear to disable and reset the pipe. table 142. upcfg0x register upcfg0x ( 1.cch ) ? usb pipe configuration 0 register 7 6 5 4 3 2 1 0 ptype1 ptype0 ptoken1 ptoken0 pepnum3 pepnum2 pepnum1 pepnum0 bit number bit mnemonic description 7-6 ptype1:0 pipe type select the type of the pipe: - 00: control - 01: isochronous - 10: bulk - 11: interrupt 5-4 ptoken1:0 pipe token select the token to associate to the pipe: - 00: setup - 01: in - 10: out - 11: reserved 3-0 pepnum3:0 pipe endpoint number set this field according to the pipe configuration. set the number of the endpoint targeted by the pipe. this value is from 0 and 15. bit number bit mnemonic description
142 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 143. upcfg1x register upcfg1x (1. cdh ) ? usb pipe configuration 1 register 7 6 5 4 3 2 1 0 - psize2 psize1 psize0 pbk1 pbk0 alloc - bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6-4 psize2:0 pipe size select the size of the pipe: - 000: 8 - 001: 16 - 010: 32 - 011: 64 - 100: 128 - 101: 256 - 110: 512 - 111: 1024 3-2 pbk1:0 pipe bank select the number of bank to declare for the current pipe. - 00: 1 bank - 01: 2 banks - 10: invalid - 11: invalid 1 alloc configure pipe memory set to configure the pipe memory with the characteristics. clear to update the memory allocation. refer to the memory management chapter for more details. 0 - reserved the value read from these bits is always 0. do not set these bits. table 144. upcfg2x register upcfg2x ( 1.cfh ) ? usb pipe configuration 2 register 7 6 5 4 3 2 1 0 intfrq7 intfrq6 intfrq5 intfrq4 intfrq3 intfrq2 intfrq1 intfrq0 bit number bit mnemonic description 7-0 intfrq7:0 interrupt pipe request frequency these bits are the maximum value in millisecond of the pulling period for an interrupt pipe. this value has no effect for a non-interrupt pipe.
143 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 145. upstax register upstax ( 1.ceh ) ? usb pipe status register 7 6 5 4 3 2 1 0 cfgok overfi underfi - dtseq1 dtseq0 nbusybk1 nbusybk0 bit number bit mnemonic description 7 cfgok configure pipe memory ok set by hardware if the required memory configuration has been successfully performed. cleared by hardware when the pipe is disabled. the usb reset and the reset pipe have no effect on the configuration of the pipe. 6 overfi overflow set by hardware when a the current pipe has received more data than the maximum length of the current pipe. an interrupt is triggered if the flerre bit is set. shall be cleared by software. setting by software has no effect. 5 underfi underflow set by hardware when a transaction underflow occurs in the current isochronous or interrupt pipe. the pipe can?t send the data flow required by the device. a zlp will be sent instead. an interrupt is triggered if the flerre bit is set. shall be cleared by software. setting by software has no effect. note: the host controller has to send a out packet, but the bank is empty. a zlp will be sent and the underfi bit is set underflow for interrupt pipe: 4 - reserved the value read from this bit is always 0. do not set this bit. 3-2 dtseq1:0 toggle sequencing flag set by hardware to indicate the pid data of the current bank: 00bdata0 01bdata1 1xbreserved. for out pipe, this value indicates the next data toggle that will be sent. this is not relative to the current bank. for in pipe, this value indicates the last data toggle received on the current bank. 1-0 nbusybk1: 0 busy bank flag set by hardware to indicate the number of busy bank. for out pipe, it indicates the number of busy bank(s), filled by the user, ready for out transfer. for in pipe, it indicates the number of busy bank(s) filled by in transaction from the device. 00ball banks are free 01b1 busy bank 10b2 busy banks 11breserved.
144 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 146. upinrqx register upinrqx ( 1.dfh ) ? usb pipe in number of request register 7 6 5 4 3 2 1 0 inrq7 inrq6 inrq5 inrq4 inrq3 inrq2 inrq1 inrq0 bit number bit mnemonic description 7-0 inrq7:0 in request number before freeze enter the number of in transactions before the usb controller freezes the pipe. the usb controller will perform (inrq+1) in requests before to freeze the pipe. this counter is automatically decreased by 1 each time a in request has been successfully performed. table 147. uperrx register uperrx ( 1.d7h ) ? usb pipe error register 7 6 5 4 3 2 1 0 - counter1 counter0 crc16 timeout pid datapid datatgl bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 counter1: 0 error counter this counter is increased by the usb controller each time an error occurs on the pipe. when this value reaches 3, the pipe is automatically frozen. clear these bits by software. 4 crc16 crc16 error set by hardware when a crc16 error has been detected. shall be cleared by software. setting by software has no effect. 3 timeout time-out error set by hardware when a time-out error has been detected. shall be cleared by software. setting by software has no effect. 2 pid pid error set by hardware when a pid error has been detected. shall be cleared by software. setting by software has no effect. 1 datapid data pid error set by hardware when a data pid error has been detected. shall be cleared by software. setting by software has no effect. 0 datatgl bad data toggle set by hardware when a data toggle error has been detected. shall be cleared by software. setting by software has no effect.
145 AT85C51SND3bx 7632a?mp3?03/06 table 148. upintx register upintx ( 1.c8h ) ? usb pipe interrupt register 7 6 5 4 3 2 1 0 fifocon nakedi rwal perri txstpi txouti rxstalli rxini bit number bit mnemonic description 7 fifocon fifo control for out and setup pipe: set by hardware when the current bank is free, at the same time than txout or txstp. clear to send the fifo data and to switch the bank. setting by software has no effect. for in pipe: set by hardware when a new in message is stored in the current bank, at the same time than rxin. clear to free the current bank and to switch to the following bank. setting by software has no effect. 6 nakedi nak handshake received set by hardware when a nak has been received on the current bank of the pipe. this triggers an interrupt if the nakede bit is set in the upienx register. shall be clear to handshake the interrupt. setting by software has no effect. 5 rwal read/write allowed out pipe: set by hardware when the firmware can write a new data into the pipe fifo. cleared by hardware when the current pipe fifo is full. in pipe: set by hardware when the firmware can read a new data into the pipe fifo. cleared by hardware when the current pipe fifo is empty. this bit is also cleared by hardware when the rxstall or the perr bit is set 4 perri pipe error set by hardware when an error occurs on the current bank of the pipe. this triggers an interrupt if the perre bit is set in the upienx register. refers to the uperrx register to determine the source of the error. automatically cleared by hardware when the error source bit is cleared. 3 txstpi setup bank ready set by hardware when the current setup bank is free and can be filled. this triggers an interrupt if the txstpe bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect. 2 txouti out bank ready set by hardware when the current out bank is free and can be filled. this triggers an interrupt if the txoute bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect. 1 rxstalli / crcerr stall received / isochronous crc error set by hardware when a stall handshake has been received on the current bank of the pipe. the pipe is automatically frozen. this triggers an interrupt if the rxstalle bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect. for isochronous pipe: set by hardware when a crc error occurs on the current bank of the pipe. this triggers an interrupt if the txstpe bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect.
146 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b 0 rxini in data received set by hardware when a new usb message is stored in the current bank of the pipe. this triggers an interrupt if the rxine bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect. table 149. upienx register upienx ( 1.d2h ) ? usb pipe interrupt enable register 7 6 5 4 3 2 1 0 flerre nakede - perre txstpe txoute rxstalle rxine bit number bit mnemonic description 7 flerre flow error interrupt enable set to enable the overfi and underfi interrupts. clear to disable the overfi and underfi interrupts. 6 nakede nak handshake received interrupt enable set to enable the nakedi interrupt. clear to disable the nakedi interrupt. 5 - reserved the value read from this bit is always 0. do not set this bit. 4 perre pipe error interrupt enable set to enable the perri interrupt. clear to disable the perri interrupt. 3 txstpe setup bank ready interrupt enable set to enable the txstpi interrupt. clear to disable the txstpi interrupt. 2 txoute out bank ready interrupt enable set to enable the txouti interrupt. clear to disable the txouti interrupt. 1 rxstalle stall received interrupt enable set to enable the rxstalli interrupt. clear to disable the rxstalli interrupt. 0 rxine in data received interrupt enable set to enable the rxini interrupt. clear to disable the rxini interrupt. table 150. updatx register updatx ( 1.d3h ) ? usb pipe data register 7 6 5 4 3 2 1 0 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 pdat1 pdat0 bit number bit mnemonic description
147 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b bit number bit mnemonic description 7-0 pdat7:0 pipe data bits set by the software to read/write a byte from/to the pipe fifo selected by pnum. table 151. upbchx register upbchx ( 1.d4h ) ? usb pipe data counter high register 7 6 5 4 3 2 1 0 - - - - - pbyct10 pbyct9 pbyct8 bit number bit mnemonic description 7-3 - reserved the value read from these bits is always 0. do not set these bits. 2-0 pbyct10:8 byte count (high) bits set by hardware. this field is the msb of the byte count of the fifo endpoint. the lsb part is provided by the upbclx register. table 152. upbclx register upbclx ( 1.d5h ) ? usb pipe data counter low register 7 6 5 4 3 2 1 0 pbyct7 pbyct6 pbyct5 pbyct4 pbyct3 pbyct2 pbyct1 pbyct0 bit number bit mnemonic description 7-0 pbyct7:0 byte count (low) bits set by the hardware. pbyct10:0 is: - (for out pipe) increased after each writing into the pipe and decremented after each byte sent, - (for in pipe) increased after each byte received by the host, and decremented after each byte read by the software.
148 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 153. upint register upint ( 1.d6h ) ? usb pipe in number of request register 7 6 5 4 3 2 1 0 - pint6 pint5 pint4 pint3 pint2 pint1 pint0 bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6-0 pint6:0 pipe interrupts bits set by hardware when an interrupt is triggered by the upintx register and if the corresponding endpoint interrupt enable bit is set. cleared by hardware when the interrupt source is served.
149 AT85C51SND3bx 7632a?mp3?03/06 audio controller the audio controller embedded in AT85C51SND3 bx is based on four functional blocks detailed in the following sections: ? the clock generator ? the audio processor ? the audio codec ? the audio dac interface figure 69. audio controller block diagram clock generator the clock generator generates the audio c ontroller clocks based on the audio clock issued by the clock controller as detailed in section ?system clock generator?, page 29 . as shown in figure 70 , it contains an audio frequencies generator able to generate the audio sampling and over-sampling frequencies fed by a normalized clock. this genera - tor is based on a pll and is entirely controlled by the audio processor depending on the encoded or decoded audio stream characteristics. figure 70. audio controller clock generator audio processor the audio processor is based on three functional blocks as shown in figure 71 . ? the audio buffer ? the digital audio processor ? the baseband processor audio codec aud clock outr outl linr linl micin micbias audio dac ddat dsel dclk oclk clock generator interface audio processor dfc bus cpu bus accken aucon.0 aud clock clock normalizing audio frequencies generator
150 AT85C51SND3bx 7632a?mp3?03/06 figure 71. audio processor block diagram audio buffer the audio buffer receives the audio data flow coming from dfc or the c51. it is based on 1 kbyte of dual-port ram. buffer description the audio buffer can be accessed in read or write mode by both c51 and dfc. access selection is done by the abacc bit in apcon1. considering the dfc, two channels can be established at the same time one in which the audio processor is the source and one in which the audio processor is the destination. to achieve such scheme, the audio buffer can be configured using absplit in apcon1 as one (see figure 72 a) or two (see figure 72 b) buffers, each containing two data packets of 512 or 256 bytes size. figure 72. audio buffer configuration internal read or write pointers can be reset at any time by setting respectively abrpr and abwpr bits in apcon1. these bits are automatically reset by hardware. buffer management the c51 reads from or writes to the buffer through the apdat register. management is controlled by a couple of flags informing the user that data can be written to the buffer or read from the buffer depending on the current operation. in case of write (audio stream decoding or codec firmware update) apreqi flag in apint is set every time a data packet (256 or 512 bytes) can be written to the buffer i.e. buffer empty or half full. apreqi is cleared when the buffer becomes full. in case of read (audio stream encoding) aprdyi flag in apint is set every time a data packet (256 or 512 bytes) can be retrieved from the buffer i.e. buffer full or half full. aprdyi is cleared when the buffer becomes empty. these flags can generate an interrupt when apreqe bit and aprdye bit in apien are respectively set (see section ?interrupts? ). audio buffer digital audio processor cpu cpu/dfc audio dac interface audio codec baseband processor cpu (apdat) cpu (apdat) dfc dfc 512-byte 512-byte cpu (apdat) dfc 256-byte rd pointer wr pointer wr pointer rd pointer 256-byte 256-byte 256-byte a. single buffer (absplit= 0) b. double buffer (absplit= 1)
151 AT85C51SND3bx 7632a?mp3?03/06 in order to avoid any spurious interrupts on the cpu side when a data transfer with the data flow controller is established, apreqe and aprdye must be left cleared. digital audio processor the digital audio processor is based on a proprietary digital signal processor. it provides capability to decode many digital audio formats like mp3, wma, g726, raw pcm? and to encode some digital audio formats like g726, raw pcm? processor initialization prior to enable the digital audio processor by setting the dapen bit in apcon1 (1) , the c51 must load the processor codec firmware which is the stream decoder or encoder. this can be achieved by setting apload (2) bit in apcon1 and loading data using the c51 (through apdat) or the dfc as detailed in the section ?audio buffer? . as soon as the codec firmware is fully loaded, the digital audio processor can be enabled with the effect to start the codec execution. then the audio stream type that can be decoded or encoded depends on the codec firmware loaded. note: 1. clearing dapen bit resets the code writing pointer address to 0000h. 2. toggling apload bit leaves the code writing pointer address unchanged. processor interface the c51 interfacing the processor through 3 registers: apcon0 by using apcmd6:0 bits, apsta and apint by using apevti bit. apcmd field is used to send commands to the processor while apsta and apevti are used by the processor to trigger an event or give a status to the c51. command and status relies on the processor codec firmware and are beyond the scope of this document. play time in order to allow time stamping in case of synchronized lyrics (karaoke mode), a 24-bit time stamp is provided by aptim2:0 registers with aptim2 being the msb and aptim0 being the lsb. time unit is millisecond. getting the time value is done by reading first aptim0, then aptim1 and aptim2. the counter value is latched during read sequence, avoiding bad reading if increment occurs. initializing the time value is done by writing first aptim0, then aptim1 and aptim2. the counter is updated after writing last time stamp byte aptim2. time value is automatically updated by the audio processor in case of fast for - ward/rewind operating mode. time value is reset when operating mode switches from stop to play mode and frozen when in pause mode. audio stream interface every codec firmwares (decoder or encoder) share a set of registers allowing to perform configuration and control and to get status from the decoding or encoding process. this set of registers is composed of ascon, the audio stream control register and assta0 assta1 and assta2, the audio stream status registers. the content of these registers depends on the codec firmware loaded and are beyond the scope of this document. baseband processor several digital baseband treatments can be applied to the digital audio signal immedi - ately before internal or external d/a conversion: ? digital volume control ? 3-bands equalizer ? bass boost effect ? virtual surround effect ? mixing mode the baseband processor is enabled by setting bpen bit in aucon. when disabled (bpen bit cleared) all of the above treatments are disabled.
152 AT85C51SND3bx 7632a?mp3?03/06 digital volume control the digital volume is controlled separately on right and left channel by setting the dvr4:0 and dvl4:0 bits respectively in aprdvol and apldvol according to table 154 . table 154. digital volume control gain note: 1. when dvr4:0 and dvl4:0 are set to mute, audio processor is still sending data to the audio codec or the audio interface with data set to the corresponding 0 value. equalizer volume control a 3-band equalizer control is provided for tone adjustment or predefined tone shapes like classic, jazz, rock? the equalizer gain is controlled in each band by programing dvb4:0 in apbdvol for the bass band, dvm4:0 in apmdvol for the medium band and dvt4:0 in aptdvol for the treble band according to table 154 . cut frequencies are defined in table 155 . in order to optimize the power consumption, the 3-band equalizer can be disabled by setting equdis in aucon. in this case the band gain control is saved but no filtering is applied. table 155. equalizer band frequency bass boost effect a bass boost effect can be established by setting bboost bit in aucon. it consists in a gain increase of +6 db in the frequency range under 200 hz. virtual surround effect a virtual surround effect can be established by setting vsurnd bit in aucon. it con - sists in applying a spatial effect to sound on both right and left channels. equalizer bar-graph an 8-band bar-graph equalizer allows dynamic audio volume report inside 8 frequency bands. to read the level of each band, first select the band by setting the eqbs2:0 bits in apebs from 000b (lowest fr equency band) to 111b (highest frequency band) then get the 5-bit band level by reading eqlev4:0 bits in apelev. dvx4:0 gain value dvx4:0 gain value dvx4:0 gain value 00000 +6 db 01011 -16db 10110 -38 db 00001 +4 db 01100 -18 db 10111 -40 db 00010 +2 db 01101 -20 db 11000 -42 db 00011 +0 db 01110 -22 db 11001 -44 db 00100 -2 db 01111 -24 db 11010 -46 db 00101 -4 db 10000 -26 db 11011 -48 db 00110 -6 db 10001 -28 db 11100 -50 db 00111 -8 db 10010 -30 db 11101 -52 db 01000 -10 db 10011 -32 db 11110 -54 db 01001 -12 db 10100 -34 db 11111 mute (1) 01010 -14 db 10101 -36 db band frequencies bass f < 750 hz medium 750 hz < f < 3300 hz treble f > 3300 hz
153 AT85C51SND3bx 7632a?mp3?03/06 mixing mode a mixing mode can be established by setting mixen bit in aucon. it consists in mixing the adc output coming from microphone or line-in inputs with the output coming from the audio processor before feeding the internal or external audio dac. signal clipping when volume controls (global + equalizer + bass boost) leads to signal saturation, out - put signal is clipped and aclipi flag is set in apint. in such case, strategy to reduce volume is under user?s firmware responsibility. aclipi flag can generate an interrupt by setting aclipe bit in apien. interrupts as shown in figure 73 , the audio processor interrupt request is generated by 8 different sources: the apreqi, aprdyi, aclipi and apgpi4:0 flags in apint. both sources can be enabled separately by using the apreqe, aprdye, aclipe and apgpe4:0 bits in apien. a global enable of the audio processor interrupt is provided by setting the eaup bit in ien0 register. the interrupt is requested each time one of the sources is asserted. figure 73. audio processor interrupt system apreqe apien.0 aprdyi apint.1 audio processor interrupt apreqi apint.0 aprdye apien.1 aclipi apint.2 request aclipe apien.2 apevti apint.3 apevte apien.3 eaup ien0.6 apgpi3:0 apint.7:4 apgpe3:0 apien.7:4
154 AT85C51SND3bx 7632a?mp3?03/06 audio codec the audio codec is controlled by four registers as detailed in figure 74 : figure 74. audio codec block diagram audio outputs AT85C51SND3b2 & AT85C51SND3b3 the audio output system of AT85C51SND3b2 & at85c 51snd3b3 is based on a pair of sigma-delta d/a converter used to convert the audio data with high linearity and high s/n. it is enabled by setting the aoen bit in accon (see table 177 ). audio input syst em features are detailed in the following sections. anti-pop circuitry in order to avoid any noise when enablin g the audio output system an anti-pop circuitry has been implemented on the audio outputs (outr and outl). it consists in a dis - charge circuit controlled by aodis bit in acaux (see table 178 ) and a preload circuit controlled by aopre bit in acaux. prior to enable the audio output system, user must take care to discharge then charge the audio outputs. output sources the audio output source can come from either the audio processor or the stereo lines inputs sources. the selection of the source is done by setting or clearing the aossel bit in accon according to table 156 . table 156. audio codec output source selection note: 1. stereo or mono choice is done by the audio processor depending on the audio flow under decoding. output gain control analog volume is controlled separately on both channel by setting the aorg4:0 bits in acorg for the right channel and the aolg4:0 bits in acolg for the left channel. table 157 shows the gain value versus the programmed aorg or aolg value. ambvs accon.6 aipg2:0 acipg.2:0 amben accon.5 aorg4:0 acorg.4:0 1 0 a d d a outr outl linr linl micin micbias to audio from audio 1 0 ailpg acipg.3 aolg4:0 acolg.4:0 0 1 d a aossel accon.1 aissel accon.4 aodrv accon.2 processor processor bias generator AT85C51SND3b2 & aossel selection 0 line input (stereo) 1 audio processor (mono or stereo) (1)
155 AT85C51SND3bx 7632a?mp3?03/06 table 157. audio codec output gain output drive control output buffers can operate in two modes depending on the power supply voltage. these are low impedance or high impedance modes. the low impedance mode is only avail - able in high power supply configuration and allows to drive a typical 32 stereo headphone, while the high impedance mode is available in low or high voltage power supply configurations and allows to drive a typical 50 k stereo amplifier. control is done by setting or clearing aodrv bit in accon according to table 158 . table 158. audio codec output drive selection audio inputs the audio input system is based on a single sigma-delta a/d converter provided for mono recording. it is enabled by setting the aien bit in accon. audio input syst em features are detailed in the following sections. inputs sources the audio input source can come from either an electret type microphone input or the stereo lines inputs sources. the selection of the source is done by setting or clearing the aissel bit in accon according to table 159 . when line inputs are selected as audio input source, stereo channels are combined together in a mono signal prior to feed the preamplifier. table 159. audio codec input source selection audio input preamplifier gain the signals coming from audio inputs goes through a preamplifier to adapt levels prior to feed the a/d converter.the preamplifier gain is controlled by aipg2:0 bits in acipg according to table 160 . table 160. audio codec input preamplifier gain aorg4:0 aolg4:0 gain value aorg4:0 aolg4:0 gain value aorg4:0 aolg4:0 gain value 00000 6 db 00111 -8 db 01110 -22 db 00001 4 db 01000 -10 db 01111 -24 db 00010 2 db 01001 -12 db 10000 -26 db 00011 0 db 01010 -14 db 10001 -28 db 00100 -2 db 01011 -16 db 10010 -30 db 00101 -4 db 01100 -18 db 10011 mute 00110 -6 db 01101 -20 db aodrv drive selection 0 low/high voltage 50 k drive 1 high voltage 32 drive aissel selection 0 line inputs 1 microphone input aipg2:0 gain value aipg2:0 gain value aipg2:0 gain value 000 0 db 010 +12 db 100 +24 db
156 AT85C51SND3bx 7632a?mp3?03/06 line inputs preamplifier gain in AT85C51SND3b2 & AT85C51SND3b3, when line inputs are selected as output source (e.g. fm decoder playback) two preamplifier gain values can be applied by set - ting or clearing ailpg bit in acipg according to table 161 . table 161. audio codec line inputs preamplifier gain microphone bias in addition, voltage supply function for an electret type microphone is integrated deliver - ing high bias (1.5v) or low bias (2v) voltage. the high bias voltage output is only available in high power supply configuration, while the low bias voltage output is avail - able in low or high voltage power supply configurations. bias voltage output is selected by ambsel bit in accon according to table 163 and is enabled by amben bit in accon according to table 162 . table 162. audio codec microphone bias control table 163. audio codec microphone bias voltage selection audio dac interface the c51 core interfaces to the audio dac interface through two special function regis - ters: adicon0 and adicon1, the audio dac interface control registers (see table 182 and table 183 ). figure 75 shows the audio interface block diagram where blocks are detailed in the fol - lowing sections. 001 +6 db 011 +18 db 101 reserved aipg2:0 gain value aipg2:0 gain value aipg2:0 gain value ailpg gain value 0 +6 db 1 +12 db amben control 0 microphone bias output disabled 1 microphone bias output enabled ambsel voltage selection 0 high bias voltage 2v output 1 low bias voltage 1.5 v output
157 AT85C51SND3bx 7632a?mp3?03/06 figure 75. audio dac interface block diagram clock controller as soon as audio dac interface is enabled by setting adien bit in adicon0, the mas - ter clock generated by the clock generator (see section ?clock generator? ) is output on the oclk pin which is the dac over-sampling clock. the over-sampling ratio is defined by overs1:0 bits in adicon0 according to table 164 and is selected depending on the dac capabilities. table 164. audio dac interface over-sampling ratio for dac compatibility, the bit clock frequency is programmable for outputting 16 bits or 32 bits per channel using the dsize bit in adicon0 (see section "data converter", page 157 ), and the word selection signal (dsel) is programmable for outputting left channel on low or high level according to cspol bit in adicon0 as shown in figure 76 . figure 76. dsel output polarity data converter the data converter block converts the audio stream coming from the audio processor to a serial format. for accepting all pcm formats and i 2 s format, just4:0 bits in adicon1 register are used to shift the data output point. as shown in figure 77 , these bits allow msb justification by setting just4:0 = 00000, lsb justification by setting just4:0 = 10000, i 2 s justification by setting just4:0 = 00001, and more than 16-bit lsb justifica - tion by filling the low significant bits with logic 0. cspol adicon0.4 aud clock 0 1 dsize adicon0.3 dsel clock controller dclk ddat oclk just4:0 adicon1.4:0 adien adicon0.0 overs1:0 adicon0.2:1 data audio data from audio processor converter overs1:0 over-sampling ratio 00 reserved 01 128 f s 10 256 f s 11 384 f s left channel right channel cspol = 1 cspol = 0 left channel right channel
158 AT85C51SND3bx 7632a?mp3?03/06 figure 77. audio output format registers dsel dclk ddat msb i2s format with dsize = 0 and just4:0 = 00001. lsb b14 msb lsb b14 b1 b1 dsel dclk ddat msb i2s format with dsize = 1 and just4:0 = 00001. lsb b14 msb lsb b14 1 2 3 13141516 1 2 3 13141516 left channel right channel 123 1718 32 123 1718 32 dsel dclk ddat b14 msb/lsb justified format with dsize = 0 and just4:0 = 00000. msb b1 b15 msb b1 lsb lsb 1 2 3 13141516 1 2 3 13141516 left channel right channel left channel right channel dsel dclk ddat 16-bit lsb justified format with dsize = 1 and just4:0 = 10000. 11618 32 32 left channel right channel 17 31 msb b14 lsb b1 msb b14 lsb b1 11618 17 31 dsel dclk ddat 18-bit lsb justified format with dsize = 1 and just4:0 = 01110. 115 3032 left channel right channel 16 31 msb b16 b2 1 b1 lsb msb b16 b2 b1 lsb 15 30 32 16 31 table 165. aucon register aucon (1.f1h) ? audio controller control register 7 6 5 4 3 2 1 0 bpen vsurnd bboost mixen equdis - - accken bit number bit mnemonic description 7 bpen baseband processor enable bit set to enable the baseband processing. clear to bypass the baseband processing and disable the baseband features. 6 vsurnd virtual surround enable bit set to enable the virtual surround effect. clear to disable the virtual surround effect. 5 bboost bass boost enable bit set to enable the bass boost effect. clear to disable the bass boost effect. 4 mixen mixing enable bit set to enable mixing of adc output with dac output. clear to disable mixing of adc output with dac output. 3 equdis equalizer disable bit set to disable the 3-band equalizer. clear to enable the 3-band equalizer.
159 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b 2-1 - reserved the value read from these bits is always 0. do not set these bits. 0 accken audio controller clock enable bit set to enable the audio controller clock. clear to disable the audio controller clock. table 166. apcon0 register apcon0 (1.f2h) ? audio processor control register 0 7 6 5 4 3 2 1 0 0 apcmd6 apcmd5 apcmd4 apcmd3 apcmd2 apcmd1 apcmd0 bit number bit mnemonic description 7 0 always 0 the value read from this bit is always 0. can not be set by software. 6-0 apcmd6:0 audio processor operating command bits codec firmware dependant. table 167. apcon1 register apcon1 (1.f3h) ? audio processor control register 1 7 6 5 4 3 2 1 0 - - abacc abwpr abrpr absplit apload dapen bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 5 abacc audio buffer access bit set to enable buffer access by c51 core. clear to enable buffer access by dfc. 4 abwpr audio buffer write pointer reset bit set to reset the audio buffer write pointer. cleared by hardware when write pointer is reset. can not be cleared by software. 3 abrpr audio buffer read pointer reset bit set to reset the audio buffer read pointer. cleared by hardware when read pointer is reset. can not be cleared by software. 2 absplit audio buffer split bit set to configure the audio buffer as a double buffer. clear to configure the audio buffer as a single buffer. bit number bit mnemonic description
160 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b 1 apload audio processor load enable bit set to enable audio processor codec code update. clear to disable audio processor codec code update. 0 dapen digital audio processor enable bit set to enable the digital audio processor. clear to disable the digital audio processor. table 168. apsta register apsta (1.eah) ? audio processor status register 7 6 5 4 3 2 1 0 apstat7 apstat6 apstat5 apstat4 apstat3 apstat2 apstat1 apstat0 bit number bit mnemonic description 7-0 apstat7:0 audio processor status byte codec firmware dependant. table 169. apint register apint (1.f4h) ? audio processor interrupt register 7 6 5 4 3 2 1 0 apgpi3 apgpi2 apgpi1 apgpi0 apevti aclipi aprdyi apreqi bit number bit mnemonic description 7-4 apgpi3:0 audio processor general purpose interrupt flag set by hardware to trigger a general purpose interrupt. cleared by hardware after writing apcon0. 3 apevti audio processor event interrupt flag set by hardware to signal an event from the audio processor. cleared by hardware after writing apcon0. 2 aclipi audio clipping interrupt flag set by hardware when audio gain (digital volume or bass boost) leads to saturation. cleared by hardware after writing apcon0. 1 aprdyi audio packet ready interrupt flag set by hardware when audio buffer has at least one data packet ready to be read (512 or 256 bytes depending on buffer configuration). cleared by hardware when audio buffer is empty. 0 apreqi audio packet request interrupt flag set by hardware when audio buffer is able to receive one data packet (512 or 256 bytes depending on buffer configuration). cleared by hardware when audio buffer is full. bit number bit mnemonic description
161 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b table 170. apien register apien (1.e9h) ? audio processor interrupt enable register 7 6 5 4 3 2 1 0 apgpe3 apgpe2 apgpe1 apgpe0 apevte aclipe aprdye apreqe bit number bit mnemonic description 7-4 apgpe3:0 audio processor general purpose interrupt enable bits set to enable the audio processor general purpose interrupt. clear to disable the audio processor general purpose interrupt. 3 apevte audio processor event interrupt enable bit set to enable the audio processor event interrupt. clear to enable the audio processor event interrupt. 2 aclipe audio clipping interrupt enable bit set to enable the audio clipping interrupt. clear to disable the audio clipping interrupt. 1 aprdye audio packet ready interrupt enable bit set to enable the audio packet ready interrupt. clear to disable the audio packet ready interrupt. 0 apreqe audio packet request interrupt enable bit set to enable the audio packet request interrupt. clear to disable the audio packet request interrupt. table 171. aptim0 register aptim0 (2.c6h) ? audio processor timer register 0 7 6 5 4 3 2 1 0 apt7 apt6 apt5 apt4 apt3 apt2 apt1 apt0 bit number bit mnemonic description 7-0 apt7:0 audio processor timer least significant byte. table 172. aptim1 register aptim1 (2.c7h) ? audio processor timer register 1 7 6 5 4 3 2 1 0 apt15 apt14 apt13 apt12 apt11 apt10 apt9 apt8 bit number bit mnemonic description 7-0 apt15:8 audio processor timer intermediate significant byte.
162 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 173. aptim2 register aptim2 (2.c9h) ? audio processor timer register 2 7 6 5 4 3 2 1 0 apt23 apt22 apt21 apt20 apt19 apt18 apt17 apt16 bit number bit mnemonic description 7-0 apt23:16 audio processor timer most significant byte. table 174. aprdvol, apldvol, apbdvol, apmdvol, aptdvol registers aprdvol, apldvol, apbdvol, apmdvol, aptdvol (2.f1h, 2.f2h, 2.f3h, 2.f4h, 2.f5h) ? audio processor right, left, bass, medium, treble digital volume registers 7 6 5 4 3 2 1 0 - - - advol4 advol3 advol2 advol1 advol0 bit number bit mnemonic description 6-5 - reserved the value read from these bits is always 0. do not set these bits. 4-0 advol4:0 digital volume refer to table 154 for information on gain control values. table 175. apebs register apebs (2.f6h) - audio processor e qualizer band select register 7 6 5 4 3 2 1 0 - - - - 0 eqbs2 eqbs1 eqbs0 bit number bit mnemonic description 7-4 - reserved the value read from these bits is always 0. do not set these bits. 3 0 always cleared this bit is permanently cleared by hardware to allow inc apebs without affecting bits 7-4. 2-0 eqbs2:0 equalizer band selection 000b: lowest frequency band to 111b highest frequency band.
163 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 176. apelev register apelev (2.f7h) - audio processor equalizer level status register 76543210 - - - eqlev4 eqlev3 eqlev2 eqlev1 eqlev0 bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4-0 eqlev4:0 equalizer audio level 00000b: min. level to 11111b: max. level. table 177. accon register accon (2.eah) ? audio codec control register 7 6 5 4 3 2 1 0 - ambsel amben aissel aien aodrv - aossel - aoen - bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 5 ambsel microphone bias select bit set to select 1.5v bias output voltage in high or low voltage configuration. clear to select 2v bias output voltage in high voltage configuration. 5 amben microphone bias enable bit set to enable the microphone bias output. clear to disable the microphone bias output. 4 aissel audio input source select bit set to select the microphone as input source. clear to select the line inputs as input source. 3 aien audio input enable bit set to enable the audio input system. clear to disable the audio input system. 2 aodrv - AT85C51SND3b2 and AT85C51SND3b3: audio output drive select bit set to select the 32 drive in high voltage configuration. clear to select the 50 k drive in high or low voltage configuration. AT85C51SND3b1: reserved the value read from this bit is always 0. do not set this bit. 1 aossel - AT85C51SND3b2 and AT85C51SND3b3: audio output source select bit set to select the audio processor as output source. clear to select the line inputs as output source. AT85C51SND3b1: reserved the value read from this bit is always 0. do not set this bit.
164 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b 0 aoen - AT85C51SND3b2 and AT85C51SND3b3: audio output enable bit set to enable the audio output system. clear to disable the audio output system. AT85C51SND3b1: reserved the value read from this bit is always 0. do not set this bit. table 178. acaux register (AT85C51SND3b2 and AT85C51SND3b3 only) acaux (2.e4h) ? audio codec auxiliary register 7 6 5 4 3 2 1 0 - - - - - - aodis aopre bit number bit mnemonic description 7-2 - reserved the value read from these bits is always 0. do not set these bits. 1 aodis audio output discharge bit set to enable the audio output discharge mechanism. clear to disable the audio output discharge mechanism. 0 aopre audio output preload bit set to enable the audio output preload mechanism. clear to disable the audio output preload mechanism. table 179. acorg register (AT85C51SND3b2 and AT85C51SND3b3 only) acorg (2.ebh) ? audio codec right output gain register 7 6 5 4 3 2 1 0 - - - aorg4 aorg3 aorg2 aorg1 aorg0 bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4-0 aorg4:0 audio output right gain refer to table 157 for gain value. bit number bit mnemonic description
165 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 180. acolg register (AT85C51SND3b2 and AT85C51SND3b3 only) acolg (2.ech) ? audio codec left output gain register 7 6 5 4 3 2 1 0 - - - aolg4 aolg3 aolg2 aolg1 aolg0 bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4-0 aolg4:0 audio output left gain refer to table 157 for gain value. table 181. acipg register acipg (2.edh) ? audio codec input preamplifier gain register 7 6 5 4 3 2 1 0 - - - - ailpg - aipg2 aipg1 aipg0 bit number bit mnemonic description 7-4 - reserved the value read from these bits is always 0. do not set these bits. 3 ailpg AT85C51SND3b2 and AT85C51SND3b3: audio input line preamplifier gain refer to table 161 for gain value. AT85C51SND3b1: reserved the value read from this bit is always 0. do not set this bit. 2-0 aipg4:0 audio input preamplifier gain refer to table 160 for gain value. table 182. adicon0 register adicon0 (2.eeh) ? audio dac interface control register 0 7 6 5 4 3 2 1 0 - - - cspol dsize overs1 overs0 adien bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4 cspol channel select dsel signal output polarity bit set to output the left channel on high level of dsel output (pcm mode). clear to output the left channel on the low level of dsel output (i 2 s mode). 3 dsize audio data size bit set to select 32-bit data output format. clear to select 16-bit data output format.
166 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 1000b reset value = 0000 0000b reset value = 0000 0000b 1-2 overs1:0 audio oversampling ratio bits refer to table 164 for bits description. 0 adien audio dac interface enable bit set to enable the audio dac interface. clear to disable the audio dac interface. table 183. adicon1 register adicon1 (2.efh) ? audio dac interface control register 1 7 6 5 4 3 2 1 0 - - - just4 just3 just2 just1 just0 bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4-0 just4:0 audio stream justification bits refer to section ?audio dac interface? for bits description. table 184. ascon register ascon (2.e1h) ? audio stream control register 7 6 5 4 3 2 1 0 asc7 asc6 asc5 asc4 asc3 asc2 asc1 asc0 bit number bit mnemonic description 7-0 asc7:0 audio stream control byte bits content depends on the audio codec firmware. table 185. assta0 register assta0 (2.e2h) ? audio stream status register 0 7 6 5 4 3 2 1 0 as0s7 as0s6 as0s5 as0s4 as0s3 as0s2 as0s1 as0s0 bit number bit mnemonic description 7-0 as0s7:0 audio stream status byte 0 bits content depends on the audio codec firmware. bit number bit mnemonic description
167 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 186. assta1 register assta1 (2.e3h) ? audio stream status register 1 7 6 5 4 3 2 1 0 as1s7 as1s6 as1s5 as1s4 as1s3 as1s2 as1s1 as1s0 bit number bit mnemonic description 7-0 as1s7:0 audio stream status byte 1 bits content depends on the audio codec firmware. table 187. assta2 register assta2 (2.e9h) ? audio stream status register 2 7 6 5 4 3 2 1 0 as2s7 as2s6 as2s5 as2s4 as2s3 as2s2 as2s1 as2s0 bit number bit mnemonic description 7-0 as2s7:0 audio stream status byte 2 bits content depends on the audio codec firmware.
168 AT85C51SND3bx 7632a?mp3?03/06 nand flash controller the AT85C51SND3bx implement a hardware nand flash controller (nfc) embedding the following features: ? up to 4 nand flash (nf) memories ? smc/xd support with up to 3 nf memories ? 512-byte, 1024-byte, 2048-byte page size support (provision for up to 8192-byte page size) ? hardware ecc support ? high speed: up to 35 ns cycle time nf support ? two separated secured memory segments: ? application segment for user codes, audio codec codes, fonts, screens? ? mass storage segment for fat formatting ? hardware write protection management for application code segment ? very high data transfer rate in read and write using dfc interface ? proprietary wear-levelling support with extremely reduced cpu load functional overview as shown in figure 78 the nfc architecture is based on six hardware units: ? the clock unit ? the control unit ? the data unit ? the security unit ? the card unit ? the interrupt unit these units are detailed in the following sections. figure 78. nfc controller block diagram nfre dfc bus nfd7:0 control nfc interrupt request unit data unit interrupt unit cpu bus nfce3:0 card unit nfwp nfwe nfale nfcle security unit nfen nfcon.0 nfc clock smins smlck
169 AT85C51SND3bx 7632a?mp3?03/06 figure 79. nand flash connection clock unit the nfc clock is generated based on the clock generator as detailed in section "dfc/nfc clock generator", page 30 . as soon as nfen bit in nfcon is set, the nfc controller receives its system clock and can then be configured. control unit the control unit configures the nfc and gives t he user all the flexibility to interface the nf devices. all the flash commands must be produced by the software, and the nfc just sends to the flash basic operations such as ?read id?, ?write a byte?, ?erase a block?, ? configuration descriptor prior to any operation, the nfc must be configured with static information concerning the nf devices connected to the product as well as other important information relevant to the desired behavior. the configuration is done by writing a descriptor byte by byte in the nfcfg register. the nf descriptor is composed of eight bytes (detailed in table 188 ). the first byte written is byte 0. after writing a descriptor, a new one can be written to the nfc. table 188. configuration descriptor content iovdd nfre nfce3:0 nfwe nfale nfcle nfd7:0 nfwp nf0 iovss wp d7:0 re we ale cle ce vss vdd nf1 wp d7:0 re we ale cle ce vss vdd nf2 wp d7:0 re we ale cle ce vss vdd nf3 wp d7:0 re we ale cle ce vss vdd 3 012 smc byte offset byte mnemonic description 0 nfpgcfg nf device page configuration register refer to table 189 for register content organization. 1 smpgcfg smc device page configuration register refer to table 189 for register content organization. 2 scfg1 sub configuration register 1 refer to table 190 for register content organization. 3 scfg2 sub configuration register 2 refer to ta b l e 191 for register content organization. 4 fpbh nf device first protected block address registers first address block of protected area. refer to section ?write protection? for detailed information. reset value is 0000 0000b, 0000 0000b. 5 fpbl 6 lpbh nf device last protected block address registers first address block of protected area. refer to section ?write protection? for detailed information. reset value is 0000 0000b, 0000 0000b. 7 lpbl
170 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0001 1110b table 189. nfpgcfg / smpgcfg registers nfpgcfg / smpgcfg ? nf / smc device page configuration registers 7 6 5 4 3 2 1 0 ndb3 ndb2 ndb1 ndb0 ndb4 - - - bit number bit mnemonic description 7-3 ndb4:0 page data number number of data bytes in a page (unit is 512 bytes). 2-0 - reserved the value read from these bits is always 0. do not set these bits. table 190. scfg1 register scfg1 ? sub configuration register 1 7 6 5 4 3 2 1 0 - numdev1 numdev0 pdev3 pdev2 pdev1 pdev0 smcen bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6-5 numdev1:0 nand flash device number write the number of devices connected (smc/xd included) minus 1. 4-1 pdev3:0 protected device configuration bits refer to table 198 for more details. 0 smcen smartmedia/xd card enable bit set to enable smc support. clear to disable smc support. table 191. scfg2 register scfg2 ? sub configuration register 2 7 6 5 4 3 2 1 0 - - - - - - bsize1 bsize0 bit number bit mnemonic description 7-2 - reserved the value read from these bits is always 0. do not set these bits.
171 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b specific action as soon as the nfc is configured, the nfc is ?idle?, i.e. ready for operation and its run - ning status flag nfrun in nfsta is cleared. the controller is ready to accept events, typically to prepare a page for read or write. as long as the nfc remains in the running state (nfrun flag set), any attempt to new event will lead to an illegal interrupt. here is the list of the possible events: writing in the nfact register as detailed in table 192 launches a specific action: ? select a device, ? begin a read data transfer (thus the spare zone will be checked), ? begin a write data transfer (thus the spare zone will be set), ? stop a data transfer before the end of a page, ?force ce low. table 192. action decoding device selection this command selects the device which will receive the next incoming events. the device number is memorized until a new device selection action is performed. dev is the device number. smc shall always be connected on device 3. table 193 summarizes the possible configurations: if dev is a device that does not comply with the configuration allowed, an illegal interrupt is triggered. 1-0 bsize1:0 block size bits write following value to specify the number of pages per block. this information is needed by the controller for the block protection management. 0 0: 32 pages per block 0 1: 64 pages per block 1 0: 128 pages per block 1 1: 256 pages per block bit number bit mnemonic description ext1:0 act2:0 launched action x x 0 0 0 no action dev 0 0 1 device selection. the device number is selected by ext. x x 0 1 0 read session. x x 0 1 1 write session. x celow 1 0 0 selected nfce signal assertion. x x 1 0 1 data transfer stop. a9 a8 1 1 0 column address extension. x x 1 1 1 reserved for future use.
172 AT85C51SND3bx 7632a?mp3?03/06 table 193. device selection allowed configuration ?read? session a ?read? session is launched and the dfc flow control is enabled. when processing the spare zone, its information will be checked. ?write? session a ?write? session is launched and the dfc flow control is enabled. when processing the spare zone, its information will be set. nfce signal force low the 512b-pages memories need to keep asserted the nfce line during the access time of a data. this can be done by setting the celow bit. in this case, the nfcex signal selected by the last ?device select? action is asserted ( nfce [dev]= l). if a new ?device select? action occurs while the celow bit is set, the nfcex signal of the old selected device is de-asserted ( nfce [old_dev]= h), and the nfcex signal of the new one is asserted ( nfce [new_dev]= l). clearing the celow bit does not force the nfce signal high: ? the nfce signal is automatically asserted at the beginning of the execution of any new commands. ? the nfce signal is automatically de-asserted at the completion of the commands. data transfer stop this action stops the nfc when the data transfer is finished. in this case, the controller state becomes ?not running? (nfrun bit cleared). this can also be used as an abort signal in streaming mode. column address extension the 512b-pages memories have different kind of read commands (00h, 01h, 50h) depending the data zone that need to be processed (1st half, 2nd half or spare). the column address given is relative to the zone chosen by the read command. the nfc needs to have the absolute column address to stop automatically at the end of the page. the column address extension is given thanks to that command. a9:8 holds the address extension. ? 00h selects the 1st half zone, i.e. the 0-255 range in the data zone. this is the default value. a read or a write in nfadc resets a9:8 to 00h. ? 01h selects the 2nd half zone, i.e. the 256-511 range in the data zone. ? 10h selects the spare zone, i.e. the 512-527 range in the data zone. smcen numdev allowed dev comment 0 0 0 1 0, 1 2 0, 1, 2 3 0, 1, 2, 3 1 0 3 (smc) no nf memory is selected 1 3 (smc), 0 2 3 (smc), 0, 1 the smlck signal can not be used in this configuration, the smlck bit is irrelevant. 3 3 (smc), 0, 1, 2 neither smlck nor smins signals can be used in this configuration. smcd and smlck bits have an irrelevant value. smcte shall be cleared.
173 AT85C51SND3bx 7632a?mp3?03/06 note that it is not possible to reset a9:8 after each command (write in nfcmd): the device status read command is used after opening a page (for read) to poll the busy status. command sending writing a command in nfcmd generates the following cycles: assembly code: mov direct, # a write in that register re-initializes the ecc engine and the ecc fifo. a read in that register returns an unexpected value. address sending writing an address in nfadc (column address) or nfadr (row address) generates the following cycles: assembly code: mov direct, # the nfadc register is used to select the column address. the nfc uses that informa - tion to build an internal byte counter in the page, thus allowing it to stop at the end of the page. 512b nf memories (ndb= 1) have 1 column cycle. other nf memories have 2 column cycles. the nfadr register is used to select the raw address, i.e. the page address. the nfc uses that information to verify if the block is protected or not. both kind of information are reset after a read of a write of the nfcmd register. a read in nfadc or nfadr returns an unexpected value. nfcex nfcle nfale nfwe nfre nfd[7:0] command nfclk / 2 address nfcex nfcle nfale nfwe nfre nfd[7:0] nfclk / 2
174 AT85C51SND3bx 7632a?mp3?03/06 data reading/writing the nfdat and nfdatf registers allow reading or writing of a byte without the use of the dfc as detailed in the section ?data unit? . it launches an immediate read or write nf cycle, depending if the software reads or writes in those registers. note: the ecc is also computed when byte are read or written via nfdat or nfdatf. ? a write in nfdat or nfdatf will produce an immediate ?write cycle? (the nf signals will be asserted accordingly) to store the byte given by the cpu. assembly code: mov direct, # ? a read of nfdatf or nfadc returns to the cpu the byte contained in that register and launches in background a new ?read c ycle? (the nf signal s will be asserted accordingly). once the ?read cycle? is completed, the byte is held in the nfdat and nfdatf or nfadc registers. ( the nfc stays in the running state (nfrun set) as long as the ?read cycle? is not performed ). note: the nfadc register is particularly suitable to read and poll the nand flash(es) status register. depending on the nand flash manufacturer, read cycle waveform may differ on the nfre pulse width parameter. in order to be compliant with all memories, nfre read pulse width can be programmed using trs bit in nfcon according to table 194 . table 194. read cycle configuration trs description 0 [1.5; 0.5] cycle nfre asserted during 1.5 clock period and deasserted during 0.5 clock period. 1 [1.0;1.0] cycle nfre asserted during 1 clock period and deasserted during 1 clock period. write data nfcex nfcle nfale nfwe nfre nfd[7:0] nfclk / 2
175 AT85C51SND3bx 7632a?mp3?03/06 assembly code: mov #, direct ? a read of nfdat returns to the cpu the byte contained in that register, but does not launch an extra background ?read cycle?. assembly code: mov #, direct in all the previous examples, the nfce line is asserted low and de-asserted at the end of the cycle. this allows minimizing the power consumption. access example figure 80 shows a read access in a 512b page. note that the nfce must be held low during the access time for that kind of memory: read data, trs cleared cpu: 40 ns setup, timing [1.5; 0.5] [15;30] ns hold nfcex nfcle nfale nfwe nfre nfd[7:0] nfclk / 2 read data, trs set cpu: 40 ns setup timing [1; 1] [15;30] ns hold nfcex nfcle nfale nfwe nfre nfd[7:0]
176 AT85C51SND3bx 7632a?mp3?03/06 figure 80. nand flash read example legend: ?? ifc cpu? illustrates the commands given by the cpu to the nfc. ? ?auto? illustrates the actions automatically launched by the nfc. ? ?ready? is the flow control line between the dfc macro and the nfc interface. ? ?busy d ? is the busy state of the device d. ? ?p? is the polling action. data unit the data unit works closely to the dfc and is responsible of all the data transfer between the nf memories and on-chip memories (usb, sram, ?). data and spare zone for management convenience, the controller is mapping a memory page as some data and spare zones. a ?data zone? is a data area composed of ndb contiguous bytes. the ?spare zone? is located after the ?data zone? until the end of the page. ndb is part of the configuration descriptor (see table 189 ) and its use is described in the following examples: ? smc page, ?512b? nf page, ?512b? xd card a page is composed of 512 contiguous data bytes (ndb= 1), followed by a spare zone of 16 bytes. ??2kb? nf page a page is composed of 1024 contiguous data bytes (ndb= 4), followed by a spare zone of 64 bytes . spare zone content the ?16-byte? spare zone contains information as specified in table 195 . ifc cpu ce d ready re busy d dev adc c adr r1 adr r2 adr r3 ce d =0 auto nfd atf nfd atf nfd atf nfd atf nfd atf nfd atf nfd atf cmd 00h cmd 00h ce d =1 manual return in read mode tr data zone spare zone (check ecc; etc...) check end of page ok must be held low during tr act (r) nfd atf ok cmd 70h cmd 70h nfd atf dum my dum my act act data zone spare zone 512 b 16 b data zone 2048 b 64 b spare zone
177 AT85C51SND3bx 7632a?mp3?03/06 table 195. spare zone content the bytes which are not managed by the nfc are written to ffh . write session the spare zone is processed after the ?data zone?. the nfc will initialize the byte at offset 3 with the byte contained in the nfudat regis - ter, and the ?logical block address? (offsets 6-7, also duplicated at offsets 11-12) with the 2-bytes-descriptor stored in nflog (see table 197, page 179 for more details). then the ecc is written at position 13, 14 and 15 for the ecc group 1 (from data byte 0 to data byte 255), and at position 8, 9 and 10 for ecc group 2 (from data byte 256 to data byte 511). the ecc used can detects 2 wrong bits or more, and correct one bit. read session the nfc does only check (depending configuration explained in the next chapter) the ecc (ecc-1 and ecc-2). spare zone management the way the spare zone is handled depends on 3 bits: the spzen bit in nfcon which is the automatic management enable bit, the eccen which is the ecc management enable bit and the eccrdye bit which is the ecc ready interrupt enable bit. table 196 summarizes the spare zone behavior according to those control bits. following section give detail on the management modes. table 196. spare zone management modes offset description 0-1 user data area. shall be managed by software. 2 ecc valid. managed by nfc. 3 user data byte. managed by nfc through nfudat register. 4 data status flag. shall be managed by software. 5 block status flag. shall be managed by software. 6-7 logical block address. managed by nfc through nflog register (see section ?logical block address? ). 8-10 ecc area-2. managed by nfc. 11-12 logical block address. managed by nfc through nflog register (see section ?logical block address? ). 13-15 ecc area-1. managed by nfc. spzen eccen eccrdye description 0 0 x spare zone management mode 1 the spare zone is not managed by the nfc. 1 1 0 spare zone management mode 2 the spare zone is entirely managed by the nfc. x 1 1 spare zone management mode 3 the spare zone is not automatically managed by the nfc. however, an interrupt is triggered when the ecc fifo is full, so after each 512 bytes processed. the user must program/verify the spare zone.
178 AT85C51SND3bx 7632a?mp3?03/06 spare zone mode 1 the spare zone is not managed by the nfc. the data zone is contiguous. the user sends the commands to prepare the page for read or write. the data flow starts when the read or write bits are set by the user (write in nfact). the nfc did not manage the spare zone, and did not stop when the ecc fifo is full. thus, nfc stops when it reaches the end of the data zone, or when it receives a stop action. spare zone mode 2 the spare zone is entirely managed by the nfc. the ecc is computed when the data flow starts. each 256 bytes met, a 3-bytes ecc is built and stored in an ecc fifo. when the ecc fifo is full, the nfc stops the flow control to the dfc, and process the spare zone (ecc, logical value, parity... described later). if the data flow stops before the end of the data zone, the user has the responsibility to stop the nfc and to program the spare zone. the nfc will stop (idle mode) when it meet the end of the page. in this case, according to necc, the controller will program/verify the appropriate spare zone(s). let?s take an example with 2kb memories: ? if the flow starts from the beginning of the page, necc is 4 and the 4 spare zones will be verified or checked ? if the flow starts at offset 512, necc is 3 and the 3 last spare zones of the page be verified or checked. ?etc. note that; ? for write session, the byte at offset 2 is written to 0 (ecc valid) when the spare zone is written. ? for read session, the ecc is verified only if the ecc is valid (byte at offset 2 is 0). this mechanism ensures that the ecc is verified when it is valid. this mode is particularly well suited for 512b and 2kb memories. for other kind of mem - ories, mode 3 is preferable. spare zone mode 3 the spare zone is not automatically managed by the nfc. the ecc is computed and stored in the ecc fifo. when the ecc fifo is full, the flow control is stopped and an interrupt is sent. the nfc returns to the idle state. for 512b memories, the eccrdyi interrupt is always triggered after 512 data bytes seen. for 2kb memories and higher memories, the eccrdyi interrupt is always triggered after 2048 data bytes seen. the ecc engine is reset after a write in the nfcmd register. necc gives the number of ecc in the fifo. depending on the mapping of the page, the user have the possibility to: ? send the right events to program/verify the spare zone (reading the ecc fifo). the read or write bits must be set (write in nfact) to resume the data transfer, until the end of the page or an stop action. the firmware shall also re-initialize the ecc fifo by writing to nfecc. 0 1 0 not supported this configuration is reserved and must not be programmed. 1 0 x not supported this configuration is reserved and must not be programmed. spzen eccen eccrdye description
179 AT85C51SND3bx 7632a?mp3?03/06 ? read the ecc fifo, (keeping the eccs in memory), re-initialize it, resume the data transfer, and to write all the ecc bytes at the end of the page. logical block address in order to automatically and properly fill t he spare zone, the logical block address must be provided to the nfc. this is done by writing a 2-bytes descriptor byte by byte to the nflog register according to table 197 . the first byte written is byte 0. the logical block addresses must be updated each time the data flow reaches the beginning of new logi - cal blocks. table 197. logical block address descriptor content reset value = 0000 0000b for each byte. in order to keep smc compatibility, lba will be organized as follow: 0 0 0 1 0 a a a a a a a a a a p header 00010b and parity ?p? are handled by software. ? a ? represents the logical block address. end of data transfer when the data transfer stops, an interrupt is sent by the dfc macro to the cpu. the cpu has then to stop the nfc macro by sending a stop action. this action can also be considered as an abort signal in a streaming mode. a stop action makes the nfc return cleanly to the idle state (nfrun cleared): it does not stop a spare area processing. end of transfer closing when the nfc stops following a stop action, in the case of a write session, the user must properly stop the page programming by copying old sectors to the new page. moreover, the spare zone shall also be managed by the software. to do this, the user needs to know where the nfc stopped: the nfbph and nfbpl registers contain the byte position of the next data to be read or written. for example, it contains 0 after a reset, and 528 if the controller stops in a 512b page after the spare zone processing. this register is incremented each time a byte is read through nfdatf or written through nfdat or nfdatf, spare zone included. a read of nfdat or nfadc does not increment the nfbp counter. the nfbp counter can be updated by software. anyway, this shall be done in debug mode, and only when the nfc is not running. moreover, the necc counter is updated when the controller reaches the end of the page. it gives the number of ecc that is ready to be written/updated. this feature shall be used when the flow does not start from the beginning of a page. for example, it con - tains 3 if the flow starts at offset 512 till the end of the page. in this situation, the three last ecc can be written/checked. security unit the security unit provides hardware mechanisms to protect nf content from any firm - ware crash and prevent data loss and provides data recovery capability through ecc management. byte offset byte mnemonic description 0 lbah logical block address (msb) . 1 lbal logical block address (lsb) .
180 AT85C51SND3bx 7632a?mp3?03/06 write protection the nfc provides a hardware mechanism to protect full or part of the memory against any spurious writing. this is achieved by using the nfwp signal and connecting it to the wp pins of the memories. the nfwp signal is automatically asserted in the following conditions: ? the internal voltage is out of specified value (brown-out detection) ? an external reset has been applied to the device ? a watchdog reset has been triggered (bad code execution) ? a write or erase to the protected area has been triggered (bad code execution) user whole memory protection the user has the possibility to protect all the flash devices (nf and smc) by asserting the external nfwp signal. this is achieved by setting the nfwp bit in nfcon. all the memories are protected at the same time, i.e. nf and smc if a smc is present. hardware protected area a user defined area in the memories (a certain amount of blocks) can be locked against writing or erasing. this is done by giving to the controller the first protected block (fpb) address, the last protected block address (lpb) and the device number to be locked (pdev). all this information is part of the configuration descriptor. table 198 summa - rizes which device is locked or not. the protected area is practically used for user firmwares, codec firmwares, fonts and other configuration data. table 198. protected device versus pdev value then, if a device is protected, the following policy is applied: ? if fpb is lower than lpb, the protected area is a contiguous area starting from fpb to lpb. ? if fpb is higher than lpb, there are two protected areas: any block address that is below lpb and any block address that is above fpb. ? if fpb is equal to lpb, all the flash is protected.this is the default behavior. pdev3 pdev2 pdev1 pdev0 description 0 0 0 0 no locked devices x x x 1 the blocks [fpb; lpb] of nf device 0 are locked x x 1 x the blocks [fpb; lpb] of nf device 1 are locked x 1 x x the blocks [fpb; lpb] of nf device 2 are locked 1 x x x the blocks [fpb; lpb] of nf device 3 (smcen=0) or of smc (smcen=1) are locked
181 AT85C51SND3bx 7632a?mp3?03/06 figure 81. nand flash write protection scheme since the nfwp signal state is part of the device status, the user can detect a fault be reading it. ecc error management when an ecc error is detected, the eccerri flag is set in nfint and the 4-byte ecc error fifo is updated. the fifo content is read byte by byte using the nferr register as detailed in table 199 . first byte of the fifo returns a status if the error can or can not be corrected. if it can no be corrected other 3-byte fifo are cleared, if it can be corrected, the following 3 bytes return the address of the byte in error within the page (2 bytes) and the address of the bit in error within the byte (1 byte). for example, if the byte read at offset 1921 (starting from 0) in a 2k page is e3 (wrong) instead of a3: ? byte offset msb will be 07h ? byte offset lsb will be 81h ? bit offset will be 06h table 199. ecc error descriptor protected fpb lpb protected fpb lpb protected fpb < lpb fpb > lpb block 0 block 0 protected fpb = lpb default block 0 fpb lpb offset description 0 error identification byte refer to table 200 for information on byte content. 1 first 256-byte group of the sector byte offset 2 second 256-byte group of the sector byte offset 3 bit offset in the byte refer to table 200 for information on byte content. table 200. ecc error identification byte 7 6 5 4 3 2 1 0 0 0 0 0 sherrid1 sherrid0 fherrid1 fherrid0
182 AT85C51SND3bx 7632a?mp3?03/06 card unit enable smartmedia or xd card management is enabled by setting smcen bit in scfg1 regis - ter as detailed in section ?configuration descriptor? where specific configuration must also be set. card detect input as shown in figure 82 the smins (smc/xd card detect) input implements an internal pull-up, in order to provide static high level when card is not present in the socket. smins level is reported by smcd bit (1) in nfsta. as soon as smc is enabled, all level modifications on smins input from h to l or from l to h (card insertion or removal) set smcti, the sm card toggle interrupt flag in nfint. note: 1. smcd bit is not relevant until smc management is enabled. figure 82. card detection input block diagram bit number bit mnemonic description 7-0 0 reserved the value read from these bits is always 0. 3-2 sherrid1-0 second half error id flag id of the error in the second ?256-byte? group of the sector. 1: correctable error. 2: not correctable error. 3: not correctable error in the ecc. anyway, the data is good. 1-0 fherrid1-0 first half error id flag id of the error in the first ?256-byte? group of the sector. 1: correctable error. 2: not correctable error. 3: not correctable error in the ecc. anyway, the data is good. table 201. ecc error identification byte 7 6 5 4 3 2 1 0 0 0 shfb2 shfb1 shfb0 fhfb2 fhfb1 fhfb0 bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. 5-3 shfb2:0 second half fail bit flag 2-0 fhfb2:0 first half fail bit flag smcti nfint.4 smins iovdd smcd nfsta.7 r pu
183 AT85C51SND3bx 7632a?mp3?03/06 card lock input as shown in figure 83 the smlck (smc/xd lock) input implements an internal pull-up, in order to provide static high level when card is not present in the socket. smlck level is reported by smlck bit (1) in nfsta register. note: 1. sdwp bit is not relevant until smc management is enabled and a card is present in the socket (smcd = 0). figure 83. card write protection input block diagram interrupt unit as shown in figure 84 , the nf controller implements five interrupt sources reported in smcti, ilgli, eccrdyi, eccerri, stopi flags in nfint register. these flags must be cleared by software when processing the interrupt service routine. all these sources are enabled separately using smcte, ilgle, eccrdye, eccerre, stope enable bits respectively in nfien register. the interrupt request is generated each time an enabled flag is set, and the global nfc controller interrupt enable bit is set (enfc in ien1 register). figure 84. nfc controller interrupt system there are 2 kinds of interrupts: processing (i.e. their generation is part of the normal pro - cessing) and exception (i.e. their generation correspond to error cases). processing interrupts are generated when: ? running to not running state transition (stopi) ? ecc ready for operation (eccrdyi) ? smc insertion or removal (smcti) exception interrupts are generated when the following events are met: ? ecc error (eccerri) smlck nfsta.6 smlck iovdd r pu nfien.4 smcte nfien.3 ilgle nfien.2 eccrdye nfien.1 eccerri nfint.3 ilgli nfc controller interrupt request enfc ien1.4 nfint.2 stopi nfint.0 eccrdyi nfint.1 eccerri nfint.4 smcti nfien.0 stope
184 AT85C51SND3bx 7632a?mp3?03/06 ? or illegal operation (ilgli) ? attempt to access a nf device which is not declared (e.g. dev= 4 while numdev= 2) ? write of events (nfdatf, nfdat, nfcmd, nfadc, nfadr) while nfc is running (nfrun= 1). note that writing in nfact while nfc is running (run=1) does not lead to an ilgli interrupt. as soon as an enabled interrupt is triggered, the nfc becomes not running (nfrun= 0). registers reset value = 0000 0000b reset value = 0000 0000b table 202. nfcfg register nfcfg ( 1.99h ) ? nand flash controller configuration register 7 6 5 4 3 2 1 0 nfgd7 nfgd6 nfgd5 nfgd4 nfgd3 nfgd2 nfgd1 nfgd0 bit number bit mnemonic description 7-0 nfgd7:0 nand flash configuration 8-byte data fifo read mode reading from this register resets the fifo manager. write mode write 8 bytes of data to update the nfc configuration registers according to table 188 . table 203. nflog register nflog ( 1.9ah ) ? nand flash controller logical block address register 7 6 5 4 3 2 1 0 nflad7 nflad6 nflad5 nflad4 nflad3 nflad2 nflad1 nflad0 bit number bit mnemonic description 7-0 nflad7:0 nand flash logical address 2-byte data fifo read mode reading from this register resets the fifo manager logical block address. write mode write 2 bytes of data (msb first) to update the nfc logical block address according to table 197 .
185 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 204. nfcon register nfcon (1.9bh) ? nand flash controller control register 76543210 - - - trs nfwp spzen eccen nfen bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4trs timing read select bit set to use timing [1; 1] for read cycle. clear to use timing [1.5; 0.5] for read cycle. 3nfwp write protect bit set to unprotect the flash devices (nfwp signal de-asserted). clear to protect the flash devices (nfwp signal asserted). 2 spzen spare zone management enable bit set to enable the spare zone management clear to disable the spare zone management. 1 eccen ecc management enable bit set to enable the ecc calculation. clear to disable the ecc calculation. 0nfen general nfc enable bit set to enable the nf controller. clear to put the nfc is in the ?suspend? state. table 205. nferr register nferr (1.9ch) ? nand flash controller ecc error information register 7 6 5 4 3 2 1 0 err7 err6 err5 err4 err3 err2 err1 err0 bit number bit mnemonic description 7-0 err7:0 error descriptor 4-byte data fifo sequential reading returns the 4-byte ecc error descriptor (see table 199 ). this register is updated following an ecc error (eccerri set). table 206. nfadr register nfadr (1.9dh) ? nand flash controller row address register 7 6 5 4 3 2 1 0 nfrad7 nfrad6 nfrad5 nfrad4 nfrad3 nfrad2 nfrad1 nfrad0 bit number bit mnemonic description 7-0 nfrad7:0 row address byte
186 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b a read of that register returns an unexpected value. reset value = 0000 0000b reset value = 0000 0000b table 207. nfadc register nfadc (1.9eh) ? nand-flash cont roller column address register 7 6 5 4 3 2 1 0 nfcad7 nfcad6 nfcad5 nfcad4 nfcad3 nfcad2 nfcad1 nfcad0 bit number bit mnemonic description 7-0 nfcad7:0 column address byte table 208. nfcmd register nfcmd (1.9fh) ? nand-flash controller command register 7 6 5 4 3 2 1 0 cmd7 cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 bit number bit mnemonic description 7-0 cmd7:0 command data byte table 209. nfact register nfact (1.a1h) ? nand-flash controller action register 7 6 5 4 3 2 1 0 - - - ext1 ext0 act2 act1 act0 bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4-3 ext1:0 extension bits refer to table 192 for the bit description. 2-0 act2:0 action bits refer to table 192 for the bit description.
187 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 210. nfdat register nfdat (1.a2h) ? nand-flash controller data access register 76543210 datd7 datd6 datd5 datd4 datd3 datd2 datd1 datd0 bit number bit mnemonic description 7-0 datd7:0 data byte writing data sends a data to the currently selected nf. reading data gets the data returned by the last read cycle. table 211. nfdatf register nfdatf (1.a3h) ? nand-flash controller data access and fetch next data register 7 6 5 4 3 2 1 0 datfd7 datfd6 datfd5 datfd4 datfd3 datfd2 datfd1 datfd0 bit number bit mnemonic description 7-0 datfd7:0 data byte writing data sends a data to the currently selected nf. reading data gets the data returned by the last read cycle and relaunch a read cycle on the currently selected nf. table 212. nfsta register nfsta (1.98h) ? nand flash controller status register 7 6 5 4 3 2 1 0 smcd smlck - nfeop necc2 necc1 necc0 nfrun bit number bit mnemonic description 7 smcd smartmediacard detection flag set by hardware when the smins input is high. cleared by hardware when the smins input is low. 6 smlck smartmedia card lock flag set by hardware when the smc is write-protected. cleared by hardware when the smc is not write-protected. 5 - reserved the value read from this bit is always 0. do not set this bit. 4 nfeop end of page flag set by hardware when the controller stops at the end of the page. clear by hardware if the controller did not reach the end of the page. 3-1 necc2:0 number of ecc bits set/clear by hardware. see section ?ecc error management? for more details.
188 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b 0 nfrun running flag set by hardware to signal that it is currently running. cleared by hardware to signal it is not running. table 213. nfecc register nfecc ( 1.a4h ) ? nand flash controller ecc 1 and ecc 2 register 7 6 5 4 3 2 1 0 nfed7 nfed6 nfed5 nfed4 nfed3 nfed2 nfed1 nfed0 bit number bit mnemonic description 7-0 nfed7:0 nand flash ecc 6-byte data fifo read mode sequential reading returns 2 ecc values of 3 bytes. write mode writing any data resets the ecc engine and the fifo manager. table 214. nfint register nfint ( 1.a5h ) ? nand flash controller interrupt register 7 6 5 4 3 2 1 0 - - - smcti ilgli eccrdyi eccerri stopi bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4 smcti smartmedia card transition interrupt flag set by hardware every time smcd bit in nfsta is toggling. shall be cleared by software. 3 ilgli illegal operation interrupt flag set by hardware when an illegal operation is performed. shall be cleared by software. 2 eccrdyi ecc ready interrupt flag set by hardware when the eccs (6 bytes) are ready for operation. this bit is set/clear even if the spare zone is automatically managed (eccen). shall be cleared by software. 1 eccerri ecc error interrupt flag set by hardware when a bad ecc is seen. shall be cleared by software. 0 stopi stop interrupt flag set by hardware when a running (nfrun= 1) to not running (nfrun= 0) transition is met (end of page, end of data transfer, ?) shall be cleared by software. bit number bit mnemonic description
189 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 215. nfien register nfien (1.a6h) ? nand flash controller interrupt enable register 7 6 5 4 3 2 1 0 - - - smcte ilgle eccrdye eccerre stope bit number bit mnemonic description 7-5 - reserved the value read from these bits is always 0. do not set these bits. 4 smcte smc transition interrupt enable bit set to enable the smcti interrupt. clear to disable the smcti interrupt. 3 ilgle illegal operation interrupt enable bit set to enable the ilgli interrupt. clear to disable the ilgli interrupt. 2 eccrdye ecc ready interrupt enable bit set to enable the eccrdyi interrupt. clear to disable the eccrdyi interrupt. 1 eccerre ecc error interrupt enable bit set to enable the eccerri interrupt. clear to disable the eccerri interrupt. 0 stope stop interrupt enable bit set to enable the stopi interrupt. clear to disable the stopi interruption. table 216. nfudat register nfudat (1.a7h) ? nand flash controller user data register 7 6 5 4 3 2 1 0 nfud7 nfud6 nfud5 nfud4 nfud3 nfud2 nfud1 nfud0 bit number bit mnemonic description 7-0 nfud7:0 nand flash user data byte user defined byte stored in byte position 3 of each spare zone.
190 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b table 217. nfbph register nfudat (1.94h) ? nand flash controller byte position (msb) register 76543210 bp15 bp14 bp13 bp12 bp11 bp10 bp9 bp8 bit number bit mnemonic description 7-0 bp15:8 nand flash position high byte most significant byte of the byte position counter. table 218. nfbpl register nfudat (1.95h) ? nand flash controller byte position (lsb) register 7 6 5 4 3 2 1 0 bp7 bp6 bp5 bp4 bp3 bp2 bp1 bp0 bit number bit mnemonic description 7-0 bp7:0 nand flash position low byte least significant byte of the byte position counter.
191 AT85C51SND3bx 7632a?mp3?03/06 mmc/sd controller the AT85C51SND3bx embed a mmc/sd controller allowing connecting of mmc and sd cards in 1-bit or 4-bit modes. for mmc, 4-bit mode rely on the mmc specification v4.0. the mmc/sd controller interfaces to the c51 core through the following special function registers: mmcon0, mmcon1, mmcon2, the three mmc control registers (see table 221 to table 223 ); mmblp, the mmc block length register (see table 224 ); mmsta, the mmc status register (see table 225 ); mmint, the mmc interrupt register (see table 226 ); mmmsk, the mmc interrupt mask register (see table 227 ); mmcmd, the mmc command register (see table 228 ); and mmdat, the mmc data register (see table 229 ). as shown in figure 85 , the mmc controller is based on four functional blocks: the clock generator that handles the sdclk (formally the mmc/sd clk) output to the card, the command line controller that handles the sdcmd (formally the mmc/sd cmd) line traf - fic to or from the card, the data line controller that handles the sddat (formally the mmc/sd dat) line traffic to or from the card, and the interrupt controller that handles the mmc controller interrupt sources. these blocks are detailed in the following sections. figure 86 shows the external components to add for connecting a mmc or a sd card to the AT85C51SND3b. sddat0 and sdcmd signals are connected to pull-up resistors. value of these resistors is detailed in the section ?dc characteristics?, page 241 . figure 85. mmc controller block diagram figure 86. mmc connection clock generator the mmc clock is generated based on the clock generator as detailed in section "mmc clock generator", page 31 . as soon as mmcen bit in mmcon2 is set, the mmc con - troller receives its system clock. the mmc command and data clock is generated on sdclk output and sent to the command line and data line controllers. command line controller as shown in figure 87 , the command line controller is divided in 2 channels: the com - mand transmitter channel that handles the command transmission to the card through the sdcmd line and the command receiver channel that handles the response recep - mmcen mmcon2.0 sdcmd sdclk dfc bus sddat3:0 command line mmc interrupt request controller data line controller interrupt controller cpu bus mmc clock r cmd iovdd sddat0 sdcmd r dat
192 AT85C51SND3bx 7632a?mp3?03/06 tion from the card through the sdcmd line. these channels are detailed in the following sections. figure 87. command line controller block diagram command transmitter for sending a command to the card, the command index (1 byte) and argument (4 bytes) must be loaded in the command transmit fifo using the mmcmd register. before starting transmission by setting the txcen bit in mmcon1 register, software must first configure: ? rxcen bit in mmcon1 register to indicate whether a response is expected or not. ? rfmt bit in mmcon0 register to indicate the response size expected. ? crcdis bit in mmcon0 register to indicate whether the crc7 included in the response will be computed or not. in or der to avoid crc error, crcdis may be set for response that do not include crc7. figure 88 summarizes the command transmission flow. the txcen flag is set until the end of transmission. the end of the command transmis - sion is signalled by the eoci flag in mmint register becoming set. this flag may generate an interrupt request as detailed in section ?interrupt? . the end of the command transmission also clears the txcen flag. command loading may be aborted by setting and clearing the ctptr bit in mmcon0 register which resets the write pointer to the transmit fifo. ctptr mmcon0.4 crptr mmcon0.5 sdcm d txcen mmcon1.0 tx command line finished state machine data converter // -> serial tx pointer rfmt mmcon0.1 crcdis mmcon0.0 rxcen mmcon1.1 data converter serial -> // rx pointer 17-byte mmcmd crc7 generator rx command line finished state machine crc7 and format checker crc7s mmsta.2 respfs mmsta.1 eoci mmint.5 eori mmint.6 command transmitter command receiver read fifo 17-byte mmcmd write fifo
193 AT85C51SND3bx 7632a?mp3?03/06 figure 88. command transmission flow command receiver the end of the response reception is signalled by the eori flag in mmint register. this flag may generate an interrupt request as detailed in section ?interrupt? . when this flag is set, 2 other flags (rxcen in mmcon1 register and crc7s in mmsta register) give a status on the response received. rxcen is cleared when the response format is cor - rect or not: the size is the one expected (48 bits or 136 bits) and a valid end bit has been received, and crc7s indicates if the crc7 computation is correct or not. the flag crc7s is cleared when a command is sent to the card and updated when the response has been received. response reading may be aborted by setting and clearing the crptr bit in mmcon0 register which resets the read pointer to the receive fifo. according to the mmc specification delay between a command and a response (for - mally n cr parameter) can not exceed 64 mmc clock periods. to avoid any locking of the mmc controller when card does not send its response (e.g. physically removed from the bus), a time-out timer must be launched to recover from such situation. in case of time-out the command controller and its internal state machine may be reset by setting and clearing the ccr bit in mmcon2 register. this time-out may be disarmed when receiving the response. command transmission load command in buffer mmcmd = index mmcmd = argument configure response rxcen = x rfmt = x crcdis = x transmit command txcen = 1
194 AT85C51SND3bx 7632a?mp3?03/06 data line controller as shown in figure 89 , the data line controller is based on a 16-byte fifo used both by the data transmitter channel and by the data receiver channel. data transfer can be handled in transmission or received by the data flow controller (see section ?data flow controller?, page 78 ) or by the c51 using mmdat register. figure 89. data line controller block diagram bus width control the data line controller supports the sd card and the new mmc 4.0 4-bit bus mode allowing higher transfer rate. the 4-bit bus width is controlled by software by setting the dbsize1:0 bits in mmcon2 register according to table 219 . in case of 1-bit bus width (card default), sddat0 is used as sddat line and sddat3:1 lines are released as i/o port. table 219. data bus size fifo implementation the 16-byte fifo is managed using 1 pointer and four flags indicating the status ready of whole or half fifo. pointer value is not accessible by software but can be reset at any time by setting and clearing dptrr bit in mmcon0 register. resetting the pointer is equivalent to abort the writing or reading of data. fifo flags indicate when fifo is ready to be read in receive mode or to be written in transmit mode. wfri is set when 16 bytes are available in writing or reading. hfri is set when 8 bytes are available. these flags are cleared when read. these flags may generate an interrupt request as detailed in section ?interrupt? . wfrs and hfrs give the status of the fifo. they are set when respectively 16 bytes or 8 bytes are ready to be read or written depending on the receive or transmit mode. datfs mmsta.3 crc16s mmsta.4 hfrs mmsta.0 hfri mmint.2 dfmt mmcon0.2 mblock mmcon0.3 datdir mmcon1.3 data converter // -> 1-bit/4-bit blen11:0 mmcon1.7:4 daten mmcon1.2 data line finished state machine data converter 1-bit/4-bit -> // dptrr mmcon0.6 tx/rx ptr wfri mmint.3 crc16 and format checker wfrs mmsta.1 eofi mmint.4 cbusy mmsta.5 sddat3 :0 dbsize1:0 mmcon2.4:3 crc16 generator mmblp7:0 eobi mmint.1 fifo 16-byte mmdat dbsize1:0 bus size 0 1-bit sddat0 data bus. 1 4-bit sddat3:0 data bus. 2-3 reserved for future use, do not program these values.
195 AT85C51SND3bx 7632a?mp3?03/06 data configuration before sending or receiving any data, the data line controller must be configured accord - ing to the type of the data transfer considered. this is achieved using the data format bit: dfmt in mmcon0 register. clearing dfmt bit enables the data stream format while setting dfmt bit enables the data block format. in data block format, the single or multi-block mode must also be configured by clearing or setting the mblock bit in mmcon0 register and the block length in bytes using blen11:0 (1) bits in mmcon1 and mmblp according to table 220 . figure 90 summarizes the data modes configuration flows. blen can have any value between 1 to 2048. table 220. block length programming note: 1. blen = 1to 2048 figure 90. data controller configuration flows data transmitter configuration for transmitting data to the card the data controller must be configured in transmission mode by setting the datdir bit in mmcon1 register. figure 91 summarizes the data stream transmission flows in both polling and interrupt modes while figure 92 summarizes the data block transmission flows in both polling and interrupt modes, these flows assume that block length is greater than 16 bytes. dfc data loading in case the data transfer is handled by the dfc, a dfc channel must be configured with the mmc controller as destination peripheral. the programmed number of data is auton - omously transferred from the source peripheral to the fifo without any intervention from the firmware. in case both fifo are empty (e.g. source peripheral busy), card clock is automatically frozen stopping card data transfer thanks to the controller automatic flow control. c51 data loading in case the data transfer is handled by the c51 (1) , data is loaded byte by byte in the fifo by writing to mmdat register. number of data loaded may vary from 1 to 16 bytes. then if necessary (more than 16 bytes to send) software must ensure that all fifo or half fifo becomes empty (wfrs or hfrs set) before loading 16 or 8 new data. in case both fifo are empty, card clock is automatically frozen stopping card data transfer thanks to the controller automatic flow control. note: 1. an enabled dfc transfer always takes precedence on a c51 transfer, it is under soft- ware responsibility not to write to mmdat register while a dfc transfer is enabled. register description mmblp7:0 block size lsb: blen11:8 mmcon1.7:4 block size msb (lsn): blen7:0 data single block configuration data stream configuration configure format dfmt = 0 data multi-block configuration configure format dfmt = 1 mblock = 1 blen11:0 = xxxh configure format dfmt = 1 mblock = 0 blen11:0 = xxxh
196 AT85C51SND3bx 7632a?mp3?03/06 data transmission transmission is enabled by setting daten bit in mmcon1 register. fifo must be filled after this flag is set. if at least the fifo is half full, data is transmitted immediately when the response to the write command has already been received, or is delayed after the reception of the response if its status is correct. in both cases transmission is delayed if a card sends a busy state on the data line until the end of this busy condition. according to the mmc specification, the data transfer from the host to the card may not start sooner than 2 mmc clock periods after the card response was received (formally n wr parameter). to address all card types, this delay can be programmed using datd1:0 bits in mmcon2 register from 3 mmc clock periods when datd1:0 bits are cleared to 9 mmc clock periods when datd1:0 bits are set, by step of 2 mmc clock periods. end of transmission in data stream mode, the end of a data frame transmission is signalled by the eofi flag in mmint register. this flag may generate an interrupt request as detailed in section ?interrupt? . it is set, after reception of the end bit. this assumes that the stop command has previously been sent to the card, which is the only way to stop stream transfer. in data single block mode, the end of a data frame transmission is signalled by the eofi flag in mmint register. this flag may generate an interrupt request as detailed in section ?interrupt? . it is set after the end of busy signal on sddat0 line. after reception of t he crc status token, two other flags in mmsta register: datfs and crc16s report a status on the frame sent. datfs indicates if the crc status token for - mat is correct or not, and crc16s indicates if the card has found the crc16 of the block correct or not. crc16s must by reset by software by sett ing dcr bit in mmcon2 register. eobi flag in mmint register is also set at the same time as eofi, and may generate an interrupt request as detailed in section ?interrupt? in data multi block mode, the end of a data frame transmission is signalled by the eofi flag in mmint register. this flag may generate an interrupt request as detailed in section ?interrupt? . it is set after the end of busy signal on sddat0 line.this assumes that the stop command has previously been sent to the card, which is the only way to stop stream transfer. the end of a block transmission is signalled by the eobi flag in mmint register. this flag may generate an interrupt request as detailed in section ?interrupt? . it is set after the end of busy signal on sddat0 line. after reception of the crc status token of a block, two other flags in mmsta register: datfs and crc16s report a st atus on the frame sent. datfs indicates if the crc sta - tus token format is correct or not, and crc16s indicates if the card has found the crc16 of the block correct or not. crc16s mu st by reset by software by setting dcr bit in mmcon2 register. busy status the card uses a busy token during a block write operation. this busy status is reported by the cbusy flag in mmsta register. the busy signal is set to 0 by the card after the crc token. at the end of busy signal, the flag daten is cleared and eofi flag is set. note: some cards do not respect mmc specification, and the busy status is reported too late on the dat0 line, considering the n st parameter. so cbusy flag is not set. in this case, sta - tus of the card must be asked with a card command.
197 AT85C51SND3bx 7632a?mp3?03/06 figure 91. data stream transmission flows send stop command data stream transmission fifo filling write 16 data to mmdat fifo empty? hfrs = 1? fifo filling write 8 data to mmdat no more data to send? start transmission daten = 1 a. polling mode data stream initialization start transmission daten = 1 data stream transmission isr fifo filling write 8 data to mmdat send stop command no more data to send? b. interrupt mode fifo empty? hfri = 1? fifo filling write 16 data to mmdat unmask fifo empty hfrm = 0 mask fifo empty hfrm = 1
198 AT85C51SND3bx 7632a?mp3?03/06 figure 92. data block transmission flows data receiver configuration to receive data from the card the data controller must be configured in reception mode by clearing the datdir bit in mmcon1 register. figure 93 summarizes the data stream reception flows in both polling and interrupt modes while figure 94 summarizes the data block reception flows in both polling and interrupt modes, these flows assume that block length is greater than 16 bytes. data reception reception is enabled by setting daten bit in mmcon1 register. the end of a data frame (block(s) or stream) reception is signalled by the eofi flag in mmint register. in multiblock mode, oebi flag signals the reception of one block. these flags may gener - ate an interrupt request as detailed in section ?interrupt? . when eofi flag is set, 2 other flags in mmsta register: datfs and crc16s give a status on the frame received. datfs indicates if the frame format is correct or not: a valid end bit has been received, and crc16s indicates if the crc16 computation is correct or not. crc16s must by reset by software by setting dcr bit in mmcon2 register. in case of data stream crc16s has no meaning and stays cleared. daten flag is cleared when eofi is set. according to the mmc specification data transmission from the card starts after the access time delay (formally n ac parameter) beginning from the end bit of the read com - mand. to avoid any locking of the mmc controller when card does not send its data (e.g. physically removed from the bus), a time-out timer must be launched to recover data block transmission fifo filling write 16 data to mmdat fifo empty? hfrs = 1? fifo filling write 8 data to mmdat no more data to send? start transmission daten = 1 a. polling mode data block initialization fifo filling write 16 data to mmdat start transmission daten = 1 data block transmission isr fifo filling write 8 data to mmdat no more data to send? b. interrupt mode fifo empty? hfri = 1? mask fifo empty hfrm = 1 unmask fifo empty hfrm = 0
199 AT85C51SND3bx 7632a?mp3?03/06 from such situation. in case of time-out, the data controller and its internal state machine may be reset by setting and clearing the dcr bit in mmcon2 register. this time-out may be disarmed after receiving 8 data (hfrs flag set) or after receiving end of frame (eofi flag set) in case of block length less than 8 data (1, 2 or 4). dfc data reading in case the data transfer is handled by the dfc, a dfc channel must be configured with the mmc controller as source peripheral. the programmed number of data is autono - mously transferred from the fifo to the destination peripheral without any intervention from the firmware. in case both fifo are full (e.g. destination peripheral busy), card clock is automatically frozen stopping card data transfer thanks to the controller automatic flow control. c51 data reading in case the data transfer is handled by the c51 (1) , data is read byte by byte from the fifo by reading mmdat register. each time fifo becomes full or half full (wfri or hfri set), software is requested to flush this fifo by reading 16 or 8data. in case fifo is full, card clock is automatically frozen stopping card data transfer thanks to the controller automatic flow control. note: 1. an enabled dfc transfer always takes precedence on a c51 transfer, it is under soft- ware responsibility not to read from mmdat register while a dfc transfer is enabled. figure 93. data stream reception flows data stream reception fifo full? hfrs = 1? fifo reading read 8 data from mmdat no more data to receive? a. polling mode data stream initialization data stream reception isr fifo reading read 8 data from mmdat send stop command no more data to receive? b. interrupt mode fifo full? hfri = 1? send stop command mask fifo full hfrm = 1 start reception daten = 1 start reception daten = 1 unmask fifo full hfrm = 0
200 AT85C51SND3bx 7632a?mp3?03/06 figure 94. data block reception flows card management card detect input as shown in figure 95 the sdins (mmc/sd card detect) input implements an internal pull-up, in order to provide static high level when card is not present in the socket. sdins level is reported by cdet bit (1) in mmsta. as soon as mmc controller is enabled, all level modifications on sdins input from h to l or from l to h (card insertion or removal) set cdeti, the card detect interrupt flag in mmint (see table 226 ). note: 1. cdet bit is not relevant until mmc controller is enabled (mmcen = 1). figure 95. card detection input block diagram card lock input as shown in figure 96 the sdlck (sd lock) input implements an internal pull-up, in order to provide static high level when card is not present in the socket. sdlck level is reported by sdwp bit (1) in mmsta register. note: 1. sdwp bit is not relevant until mmc controller is enabled (mmcen = 1) and a card is present in the socket (cdet = 0). data block reception start transmission daten = 1 fifo full? hfrs = 1? fifo reading read 8 data from mmdat no more data to receive? a. polling mode data block initialization start reception daten = 1 data block reception isr fifo reading read 8 data from mmdat no more data to receive? b. interrupt mode fifo full? hfri = 1? mask fifo full hfrm = 1 unmask fifo full hfrm = 0 cdeti mmint.7 sdins iovdd cdet mmsta.6 r pu
201 AT85C51SND3bx 7632a?mp3?03/06 figure 96. sd card write protection input block diagram interrupt as shown in figure 97 , the mmc controller implements eight interrupt sources reported in cdeti, eori, eoci, eofi, wfri, hfri and eobi flags in mmcint register. these flags are detailed in the previous sections. all these sources are maskable separately using cdetm, eorm, eocm, eofm, wfrm, hfrm and eobm mask bits respectively in mmmsk register. the interrupt request is generated each time an unmasked flag is set, and the global mmc controller interrupt enable bit is set (emmc in ien1 register). reading the mmint register automatically clears the interrupt flags (acknowledgment). this implies that register content must be saved, and tested flag by flag to be sure not to forget any interrupts. figure 97. mmc controller interrupt system sdwp mmsta.7 sdlck iovdd r pu hfrm mmmsk.2 eofm mmmsk.4 eorm mmmsk.6 mmc interrup t cdeti mmint.7 eocm mmmsk.5 emmc ien1.5 cdetm mmmsk.7 eofi mmint.4 wfrm mmmsk.3 eori mmint.6 wfri mmint.3 eoci mmint.5 eobm mmmsk.1 hfri mmint.2 eobi mmint.1 reques t
202 AT85C51SND3bx 7632a?mp3?03/06 registers reset value = 0000 0010b table 221. mmcon0 register mmcon0 (1.b1h) ? mmc control register 0 7 6 5 4 3 2 1 0 - dptrr crptr ctptr mblock dfmt rfmt crcdis bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit 6 dptrr data pointer reset bit set to reset the read and write pointer of the data fifo. cleared by hardware after pointer reset is achieved. 5 crptr command receive pointer reset bit set to reset the read pointer of the receive command fifo. cleared by hardware after pointer reset is achieved. 4 ctptr command transmit pointer reset bit set to reset the write pointer of the transmit command fifo. cleared by hardware after pointer reset is achieved. 3 mblock multi-block enable bit set to select multi-block data format. clear to select single block data format. 2 dfmt data format bit set to select the block-oriented data format. clear to select the stream data format. 1 rfmt response format bit set to select the 48-bit response format. clear to select the 136-bit response format. 0 crcdis crc7 disable bit set to disable the crc7 computation when receiving a response. clear to enable the crc7 computation when receiving a response. table 222. mmcon1 register mmcon1 (1.b2h) ? mmc control register 1 7 6 5 4 3 2 1 0 blen3 blen2 blen1 blen0 datdir daten respen cmden bit number bit mnemonic description 7-4 blen11:8 block length bits refer to ta b l e 220 for bits description. 3 datdir data direction bit set to select data transfer from host to card (write mode). clear to select data transfer from card to host (read mode).
203 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = 0000 0000b 2 daten data transfer enable bit set to enable data transmission or reception immediately or after response has been received. cleared by hardware after the crc reception in reception mode or after the busy status if any in transmission mode. 1 rxcen response command enable bit set to enable the reception of a response following a command transmission. cleared by hardware when response is received. 0 txcen command transmission enable bit set to enable transmission of the command fifo to the card. cleared by hardware when command is transmitted. table 223. mmcon2 register mmcon2 (1.b3h) ? mmc control register 2 7 6 5 4 3 2 1 0 fck dcr ccr dbsize1 dbsize0 datd1 datd0 mmcen bit number bit mnemonic description 7 fck mmc force clock bit set to enable the mclk clock out permanently. clear to disable the mclk clock and enable flow control. 6 dcr data controller reset bit set to reset the data line controller in case of transfer abort, or to reset crc16s bit after an error occurs. cleared by hardware after the data line controller reset is achieved. 5 ccr command controller reset bit set to reset the command line controller in case of transfer abort. cleared by hardware after the data line controller reset is achieved. 4-3 dbsize1:0 data bus size refer to ta b l e 219 for bits description. 2-1 datd1:0 data transmission delay bits used to delay the data transmission after a response from 3 mmc clock periods (all bits cleared) to 9 mmc clock periods (all bits set) by step of 2 mmc clock periods. 0 mmcen mmc clock enable bit set to enable the mmc clocks and activate the mmc controller. clear to disable the mmc clocks and freeze the mmc controller. table 224. mmblp register mmcon2 (1.b4h) ? mmc block length lsb register 7 6 5 4 3 2 1 0 blen7 blen6 blen5 blen4 blen3 blen2 blen1 blen0 bit number bit mnemonic description
204 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b reset value = xx00 0000b, depends wether a card is present in the socket or not and if it is locked or not. bit number bit mnemonic description 7-0 blen7:0 block length lsb refer to ta b l e 220 for byte description table 225. mmsta register mmsta (1.b5h read only) ? mmc status register 7 6 5 4 3 2 1 0 sdwp cdet cbusy crc16s datfs crc7s wfrs hfrs bit number bit mnemonic description 7 sdwp sd card write protect bit set by hardware when the sd card socket wp switch is opened. cleared by hardware when the sd card socket wp switch is closed. 6 cdet card detection bit set by hardware when the sd card socket presence switch is opened. cleared by hardware when the sd card socket presence switch is closed. 5 cbusy card busy flag set by hardware when the card sends a busy state on the data line. cleared by hardware when the card no more sends a busy state on the data line. 4 crc16s crc16 status bit transmission mode set by hardware when the token response reports a bad crc. cleared by software by setting dcr bit in mmcon2. reception mode set by hardware when the crc16 received in the data block is not correct. cleared by software by setting dcr bit in mmcon2. 3 datfs data format status bit transmission mode set by hardware when the format of the token response is correct. cleared by hardware when the format of the token response is not correct. reception mode set by hardware when the format of the frame is correct. cleared by hardware when the format of the frame is not correct. 2 crc7s crc7 status bit set by hardware when the crc7 computed in the response is correct. cleared by hardware when the crc7 computed in the response is not correct. this bit is not relevant when crcdis is set. 1 wfrs whole fifo ready status bit set by hardware when 16 bytes can be read in receive mode or written in transmit mode. cleared by hardware when fifo is not ready. 0 hfrs half fifo ready status bit set by hardware when 8 bytes can be read in receive mode or written in transmit mode. cleared by hardware when fifo is not ready.
205 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 226. mmint register mmint (1.beh read only) ? mmc interrupt register 7 6 5 4 3 2 1 0 cdeti eori eoci eofi wfri hfri eobi - bit number bit mnemonic description 7 cdeti card detection interrupt flag set by hardware every time cdet bit in mmsta is toggling. cleared when reading mmint. 6 eori end of response interrupt flag set by hardware at the end of response reception. cleared when reading mmint. 5 eoci end of command interrupt flag set by hardware at the end of command transmission. cleared when reading mmint. 4 eofi end of frame interrupt flag set by hardware at the end of frame (stream, single block or multi block) transfer. clear when reading mmint. 3 wfri whole fifo ready interrupt flag set by hardware when 16 bytes can be read in receive mode or written in transmit mode. cleared when reading mmint. 2 hfri half fifo ready interrupt flag set by hardware when 8 bytes can be read in receive mode or written in transmit mode. cleared when reading mmint. 1 eobi end of block interrupt flag set by hardware at the end of block (single block or multi block) transfer. cleared when reading mmint. 0 - reserved the value read from this bit is always 0. do not set this bit. table 227. mmmsk register mmmsk (1. bfh ) ? mmc interrupt mask register 7 6 5 4 3 2 1 0 mcbm eorm eocm eofm wfrm hfrm eobm - bit number bit mnemonic description 7 cdetm card detection interrupt mask bit set to prevent cdeti flag from generating an interrupt. clear to allow cdeti flag to generate an interrupt.
206 AT85C51SND3bx 7632a?mp3?03/06 reset value = 1111 1110b reset value = 1111 1111b reset value = 1111 1111b 6 eorm end of response interrupt mask bit set to prevent eori flag from generating an interrupt. clear to allow eori flag to generate an interrupt. 5 eocm end of command interrupt mask bit set to prevent eoci flag from generating an interrupt. clear to allow eoci flag to generate an interrupt. 4 eofm end of frame interrupt mask bit set to prevent eofi flag from generating an interrupt. clear to allow eofi flag to generate an interrupt. 3 wfrm whole fifo ready interrupt mask bit set to prevent wfri flag from generating an interrupt. clear to allow wfri flag to generate an interrupt. 2 hfrm half fifo ready full interrupt mask bit set to prevent hfri flag from generating an interrupt. clear to allow hfri flag to generate an interrupt. 1 eobm end of block interrupt mask bit set to prevent eobi flag from generating an interrupt. clear to allow eobi flag to generate an interrupt. 0 - reserved the value read from this bit is always 0. do not set this bit. table 228. mmcmd register mmcmd (1.b7h) ? mmc command register 7 6 5 4 3 2 1 0 mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 bit number bit mnemonic description 7-0 mc7:0 mmc command receive byte output (read) register of the response fifo. mmc command transmit byte input (write) register of the command fifo. table 229. mmdat register mmdat (1.b6h) ? mmc data register 7 6 5 4 3 2 1 0 md7 md6 md5 md4 md3 md2 md1 md0 bit number bit mnemonic description 7-0 md7:0 mmc data byte input (write) or output (read) register of the data fifo. bit number bit mnemonic description
207 AT85C51SND3bx 7632a?mp3?03/06 parallel slave interface the AT85C51SND3bx implement a parallel slave interface (psi) allowing parallel con - nection with a host for remote control and data transfer. by using this interface, the AT85C51SND3bx can be seen as a multimedia co-processor and be remotely con - trolled by the host. the main features of the psi interface are: ? arm / i80 glueless interface capability ? 8-bit parallel data bus ? 1-bit address bus ? 16-byte fifo with mcu interrupt capability ? bi-directional multimedia bus connection through one dfc channel figure 98 shows a typical psi host connection. interface consists in a 8-bit data bus, a 1-bit address bus and read and write signals along with a chip select. figure 98. typical psi host connection description the c51 core interfaces with the psi using the following special function registers: psicon (see table 231 ) the control register, psista (see table 232 ) the status regis - ter, psidat (see table 233 ) the data register and psisth (see table 234 ) the host status register. the psi is enabled by setting the psen bit in psicon. as soon as the psi is enabled, i/o ports are programmed in input and i/o pull-ups are disabled. figure 99. psi block diagram sd7:0 AT85C51SND3b a0 d7:0 rd host srd swr wr sa0 scs csx px.y intx note: 1. optional signal for slave to host signaling. (1) control manager swr sa0 dfc bus sd7:0 slave decoder data manager interrupt controller cpu bus srd scs psi interrupt request 16-byte fifo per clock
208 AT85C51SND3bx 7632a?mp3?03/06 psi addressing the AT85C51SND3bx are accessible by a host in read or write at two different address locations by setting or clearing the sa0 address signal. the data management is detailed in following sections and differs depending on sa0 level. table 234 shows the addressing truth table. figure 100 and figure 101 show the read and write host cycles. table 230. psi addressing truth table figure 100. host read waveforms figure 101. host write waveforms write data sampling in order to be compliant with hosts depending on write cycle timing, a delay from srw signal assertion can be programmed for sampling data written by the host. this delay is programmable from 0 to 7 peripheral clock periods using psws2:0 bits in psicon. fig - ure 102 shows the write sampling delay waveform. depending on the system clock frequency, host may need to add wait states inside read or write cycles. sa0 srd / swr selection 1 read host reads the psisth register to get psi status from both hardware and software. 1 write host writes in the fifo. 0 read dfc transfer (psi is destination) host reads data from the source peripheral through the fifo. cpu transfer host reads data from the fifo. 0 write dfc transfer (psi is source) host writes data to the destination peripheral through the fifo. cpu transfer host writes data in the fifo. read data sa0 sd7:0 srd read psisth scs sa0 sd7:0 swr data write scs data write
209 AT85C51SND3bx 7632a?mp3?03/06 figure 102. write data sampling configuration ?sa0= h? mode the ?sa0= h? mode is particularly fitting control management over a protocol. figure 103 shows a data cycle from host to device. prior to send any data bytes, the host must take care of the psi state by reading the AT85C51SND3bx with sa0 signal set. this returns psisth: the host status register content. while pshbsy bit in psisth is set, the host must not start sending data. as soon as pshbsy bit is released, the host can send up to 16 bytes of data. first data writing automatically sets psbsy flag in psista and cons equently pshbsy bit so that host knows that system is now busy and processing. an interrupt can be gen - erated when psbsy flag is set by enabling psbsye bit in psicon while global psi interrupt is enabled in ien1 (see figure 104 ). the software can start reading and process the data after first byte reception. as soon as data processing is done, psbsy flag is cleared and consequently pshbsy bit so that host knows that system has finished processing. a software status can have been previously written to psisth for reporting to the host. note: if software reading is quicker than host writing, psempty bit must be polled before read - ing new data byte. figure 103. data management (sa0 = h) ?sa0= l? mode the ?sa0= l? mode is particularly fitting data transfer with huge amount of data. trans - fer can be done in read and write using the dfc for high throughput or the cpu. after control processing (psbsy cleared) and relying to the protocol, the host starts transfer - ring data. in all cases the host which is the master controls the data transfer by reading from or writing to the slave. cpu transfer in case of transfer handled by the cpu, the data transfer is done byte by byte. as the host runs usually quicker than the slave, a software handshake must be established to avoid underrun or overrun condition. dfc transfer in case of transfer handled by the dfc, the slave can acknowledge its control process - ing (psbsy cleared) as s oon as destination (host write) or source (host read) is ready. swr scs per clk sd7:0 write data data sampling psws2:001234567 host write psbsy sa0 = h up to 16 bytes psempty cpu read clear psbsy software treatment
210 AT85C51SND3bx 7632a?mp3?03/06 host can then read or write by burst an amount of data defined by the protocol (see section ?data flow controller?, page 78 ). in order to avoid any underrun or overrun condition during burst transfer, host must be slower than the dfc destination peripheral (host write) or the dfc source peripheral (host read). overrun - underrun conditions an overrun condition occurs when the hosts writes data quicker than the slave can con - sume it. an underrun condition occurs when the host read data quicker than the slave can deliver it. as soon as one of these two conditions is triggered, the psrun flag in psista is set. an interrupt can be generated when psrun bit is set by enabling psrune bit in psi - con while global psi interrupt is enabled in ien1 (see figure 104 ). notes: 1. overrun and underrun conditions may appear in both transfer modes (cpu or dfc). 2. in overrun condition, the data written by the host is discarded. 3. in underrun condition, the data read by the host is the same as the previous one. interrupts as shown in figure 104 , the psi implements two interrupt sources reported in psbsy and psrun flags in psista. these flags ar e detailed in the pr evious sections. these sources are enabled separately using psbsye, and psrune enable bits respectively in psicon. the interrupt request is generated each time an enabled flag is set, and the global psi interrupt enable bit is set ( epsi in ien1 register). figure 104. psi controller interrupt system psbsye psicon.6 psi interrupt psbsy psista.6 epsi ien1.2 psrune psicon.5 psrun psista.5 request
211 AT85C51SND3bx 7632a?mp3?03/06 registers reset value = 0000 0000b table 231. psicon register psicon (1.adh) ? psi control register 7 6 5 4 3 2 1 0 psen psbsye psrune psws2 psws1 psws0 - - bit number bit mnemonic description 7 psen interface enable bit set to enable the psi controller. clear to disable the psi controller. 6 psbsye busy interrupt enable bit set to enable the busy interrupt. clear to disable the busy interrupt. 5 psrune overrun/underrun interrupt enable bit set to enable the overrun interrupt. clear to disable the overrun interrupt. 4-2 psws2:0 write sampling bits data write sampling wait states after wr signal assertion from 1 clock up to 7 clock periods 1-0 - reserved the value read from these bits is always 0. do not set these bits. table 232. psista register psista (1.aeh) ? psi status register 7 6 5 4 3 2 1 0 psempty psbsy psovr psrdy - - - - bit number bit mnemonic description 7 psempty fifo empty flag set by hardware when the fifo is empty. cleared by hardware when at least one data byte is present in the fifo. 6 psbsy busy flag set by hardware when the fifo becomes not empty (host has sent data with sa0 = h). can be set or cleared by software. 5 psrun overrun/underrun flag overrun set by hardware when the host sends a data and the fifo is full. clear by software to acknowledge the overrun condition. underrun set by hardware when the host reads a data and the fifo is empty. clear by software to acknowledge the underrun condition. 4 psrdy ready flag set by hardware when a data is ready to be sent to the host. cleared by hardware at the end of a host read cycle.
212 AT85C51SND3bx 7632a?mp3?03/06 reset value = 1000 0000b reset value = 0000 0000b reset value = 0000 0000b 3-0 - reserved the value read from these bits is always 0. do not set these bits. table 233. psisth register psisth (1.ach) ? psi host status register 7 6 5 4 3 2 1 0 pshbsy pssth6 pssth5 pssth4 pssth3 pssth2 pssth1 pssth0 bit number bit mnemonic description 7 pshbsy interface busy flag host access (read with sa0 = h) copy of the psbsy flag. software access always returned as logic 0. can not be written by software. 6-0 pssth6:0 7-bit host status data set by software to report status to the host. table 234. psidat register psidat (1.afh) ? psi data register 7 6 5 4 3 2 1 0 psd7 psd6 psd5 psd4 psd3 psd2 psd1 psd0 bit number bit mnemonic description 7-0 psd7:0 data bits reading this register returns the data written by the host in the fifo. writing this register set data in the fifo read later by the host. bit number bit mnemonic description
213 AT85C51SND3bx 7632a?mp3?03/06 serial i/o port the AT85C51SND3bx implement a serial input/output port (sio) allowing serial com - munication. by using this interface, the AT85C51SND3b can be seen as a multimedia co-processor and be remotely controlled by the host. the main features of the sio interface are: ? asynchronous mode (uart: rx, tx) ? hardware flow control ( cts , rts ) ? high speed baud rate generator ? 16-byte input buffer with mcu interrupt capability ? bi-directional multimedia bus connection through one dfc channel figure 105 shows a typical sio host connection. interface consists in a 2-bit receive/transmit bus and a 2-bit flow control bus. figure 105. typical sio host connection description the c51 core interfaces with the sio using the following special function registers: scon, the sio control register (see table 242 ); sfcon, the sio flow control register (see table 243 ); sint, the sio interrupt source register (see table 244 ); sien, the sio interrupt enable register (see table 245 ); sbuf, the sio buffer register (see table 246 ); sbrg0, sbrg1 and sbrg2, the sio baud rate generator registers (see table 247 to table 249 ). as shown in figure 106 the sio is based on three main functional blocks detailed in the following sections: the baud rate generator that generates an over - sampling clock for both receiver and transmitter, the receiver that handles the characters reception and the transmitter that handles the characters transmission. data transfer the data transfers can be handled completely by the c51 in full duplex, i.e. c51 man - ages character transmission by writing data to sbuf register and character reception by reading data from sbuf. it is obvious that using c51 for data transfer leads to low throughput. in order to increase throughput and take advantage of high bit rates up to 8mbit/s, a dfc channel can be associated to the sio in read or write (see section ?data flow controller?, page 78 ). dfc can be used used for data reception (sio considered as source) or data transmission (sio considered as destination). in both cases, the data transfer is still full duplex since c51 continues to handle transmission or reception but at lower throughput. table 235 summarizes the data transfer modes association. dfc usage is enabled as soon as a dfc transfer is enabled by selecting sio as source or destination. table 235. data transfer modes txd AT85C51SND3b rts txd rxd host rxd cts cts rts transfer modes reception handling transmission handling high throughput reception dfc (sio is source) c51 high throughput transmission c51 dfc (sio is destination) low throughput transfer (default) c51 c51
214 AT85C51SND3bx 7632a?mp3?03/06 figure 106. sio block diagram character format the character consists of five fields: start, data, parity, stop and guard fields. figure 107 shows a character example with 8 data bits, 1 parity bit, 2 stop bits and 2 guard bits. figure 107. character format example start field the start field is fixed and composed of 1 bit transmitted or received at low level. data field the data field is composed of 7 or 8 bits by programming dlen bit in scon according to table 236 . the least significant bit is always first transmitted. table 236. data bit number selection parity field the parity field is optional and enabled by pben bit in scon. this field is composed of 1 bit and its mode is programmable by pmod1:0 bits in scon according to table 237 . table 237. parity mode selection stop field the stop field is composed of 1 or 2 bits transmitted or received at high level by pro - gramming stop bit in scon according to table 238 . rxd cts dfc cpu rts txd sio interrupt request sio clock baud rate generator receiver transmitter interrupt controller bus bus d3 d0 d1 data stop 1 parity stop 2 d2 d4 d5 d6 d7 p 2 guard bits start char n inter-char char n+1 dlen description 0 7-bit data length. 1 8-bit data length. pmod1 pmod0 description 0 0 mark: high level 0 1 space: low level 1 0 even: high level if the number of bits at high level in the data field is even. 1 1 odd: low level if the number of bits at high level in the data field is odd.
215 AT85C51SND3bx 7632a?mp3?03/06 table 238. stop bit number selection guard field the guard field is not part of a character and is an optional inter-character spacing com - posed of 0 to 3 bits transmitted at high level by programming gbit1:0 bits in scon according to table 239 . the guard field allows transmitter to be compliant with con - nected host (overrun avoiding) and is emitted after the last stop bit of a character. table 239. guard field size selection baud rate generator the baud rate generator is fed by the sio clock as detailed in section ?sio clock gen - erator?, page 32 . the maximum baud rate can be achieved by selecting the high frequency issued by a division of the pll clock. the clock generated is an oversampling clock. the oversampling factor is programmable using ovrsf3:0 bits in sfcon with oversampling factor equal to ovrsf3:0 + 1 (e.g.: ovrsf3:0= 11 for a 12x oversampling). baud rate calculation as shown in figure 109 , the baud rate generator is composed of an integer divider fol - lowed by a fractional divider. the baud rate formula is given by figure 108 . in this formula, variables must be chosen as followed: ? ovrsf the oversampling factor depends mainly on the frequency and the quality of the medium transporting the data. in any case, ovsf3:0 must not be less than 4 for proper majority vote in bit reception. ?adiv must be greater than bdiv and less than (k ? ovrsf). k being the number of bit in a character (from 9 to 11). ?bdiv must be greater than 1/ according to the tolerance on the real baud rate br r compare to the theoretical baud rate br t . being the error: = k ? |1/bb t - 1/br r |. table 240 shows some programming values depending on the sio frequency and con - sidering an oversampling factor of 12 (oversf3:0= 11). figure 108. baud rate formula stop description 0 1 stop bit. 1 2 stop bits. gbit1 gbit0 description 0 0 0 guard bit inserted (default). 0 1 1 guard bit inserted. 1 0 2 guard bits inserted. 1 1 3 guard bits inserted. baud_rate= adiv ? cdiv ? ovrsf f sio ? bdiv
216 AT85C51SND3bx 7632a?mp3?03/06 figure 109. baud rate generator block diagram table 240. baud rate generator value (12x oversampling) note: 1. this high frequency available through the clock generator requires pll usage. it is recommended to use it only for high baud rate that can not be achieved using oscilla- tor frequency. baud rate f sio = 12 mhz f sio = 16 mhz f sio = 20 mhz f sio = 24 mhz f sio = 120 mhz (1) a b c % a b c % a b c % a b c % a b c % 9600 125 6 5 0 110 99 125 0 124 5 7 0.007 125 3 5 0 110 15 142 0.033 19200 125 12 5 0 125 9 5 0 124 10 7 0.007 125 6 5 0 110 49 232 0.004 38400 125 24 5 0 125 18 5 0 124 20 7 0.007 125 12 5 0 110 49 116 0.004 57600 125 36 5 0 125 27 5 0 124 30 7 0.007 125 18 5 0 124 5 7 0.007 115200 125 72 5 0 125 54 5 0 124 60 7 0.007 125 36 5 0 124 10 7 0.007 230400 115 53 2 0.016 125 108 5 0 120 83 5 0.067 125 72 5 0 217 5 1 0.007 460800 115 53 1 0.016 120 83 2 0.067 112 31 1 0.111 115 53 2 0.016 217 10 1 0.007 921600 115 106 1 0.016 120 83 1 0.067 112 62 1 0.111 115 53 1 0.016 118 87 8 0.002 1m 1 1 1 0 112 84 1 0 115 69 1 0 110 55 1 0 120 12 1 0 1.5m - - - - - - - - 110 99 1 0 112 84 1 0 120 18 1 0 2m - - - - - - - - - - - - 1 1 1 0 115 23 1 0 4m - - - - - - - - - - - - - - - - 115 46 1 0 8m - - - - - - - - - - - - - - - - 115 92 1 0 adiv7:0 sbrg1 bdiv7:0 sbrg2 fractional post-divider a b cdiv7:0 sbrg0 to serial receiver & integer pre-divider c sio clock sbrg clock transmitter
217 AT85C51SND3bx 7632a?mp3?03/06 receiver as shown in figure 110 , the receiver is based on a character handler taking care of character integrity check and feeding the reception shift register filling itself a 16-byte data fifo managed by the fifo and flow controller. figure 110. receiver block diagram flow control the reception flow can be controlled by hardware using the rts pin. the goal of the flow control is to inform the external transmitter when the rx fifo is full of a certain amount of data. thus the transmitter can stop sending characters. rts usage and so associated flow control is enabled using rtsen bit in sfcon. to support transmitter that has stop latency, a threshold can be programmed to allow characters reception after rts has been deasserted. the threshold can be pro - grammed using rtsth1:0 in sfcon according to table 241 . as soon as enough data has been read from the rx fifo, rts is asserted again to allow transmitter to continue transmission. to avoid any glitch on rts signal, an hysteresis on 1 data is imple - mented. figure 111 shows a reception example using a threshold of 4 data and a host transmit - ter latency of 3 characters. figure 111. reception flow control waveform example table 241. rts deassertion threshold ri sint.0 rtsen scon.2 oversf3:0 sfcon.7:4 brg clock rxd rx shift reg rtsth1:0 scon.1:0 fifo & flow controller sbuf rx 16-byte fifo rts character handler fei sint.2 pei sint.3 oei sint.4 rtsth1 rtsth0 description 0 0 rts deasserted when rx fifo is full. 0 1 rts deasserted when 2 data can still be loaded in rx fifo. 1 0 rts deasserted when 4 data can still be loaded in rx fifo. 1 1 rts deasserted when 8 data can still be loaded in rx fifo. c20 rts rxd c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 0 1 2 3 4 5 6 7 8 9 10 11 fifo c13 c14 c15 12 13 c16 c17 c18 c19 14 15 14 13 12 10 11 cpu read 11 12 13 15 index 14 host stop host stop latency latency
218 AT85C51SND3bx 7632a?mp3?03/06 receiver errors there are three kinds of errors that can be set during character reception: the framing error, the parity error, and the overrun error detailed in the following sections. framing error a framing error occurs when the stop field of a received character is not at high level. framing error is reported in fei flag in sint. framing error condition is acknowledged by clearing the fei flag. parity error a parity error occurs when the parity field of a received character does not matches the programmed one in pmod1:0 bits. parity error is reported in pei flag in sint. parity error condition is acknowledged by clearing the pei flag. overrun error an overrun error occurs when a character is received while the rx shift register is full (rx fifo full). in this case, received character is discarded. overrun error is reported in oei flag in sint. overrun error condition is acknowledged by clearing the oei flag. note: in case of data burst reception, the error flags report an error within the data burst. it is obvious to discard the whole data burst and to handle the errors by the protocol (retry?). transmitter as shown in figure 112 , the transmitter is based on a character handler taking care of character transmission and fed by the transmission shift register filled itself by a 1-byte data fifo managed by the fifo and flow controller. figure 112. transmitter block diagram flow control the transmission flow can be controlled by hardware using the cts pin controlled by the external receiver. the goal of the flow control is to stop transmission when the receiver is full of data. cts usage and so associated flow control is enabled using ctsen bit in sfcon. the transmitter stop latency may vary from 0 to a maximum of 1 character, meaning that transmission always stops at the end of the character under transmission if any. interrupts as shown in figure 113 , the sio implements five interrupt sources reported in ri, ti, fei, pei, oei and eoti flags in sint. these flags are detailed in the previous sections. these sources are enabled separately using rie, tie, feie, peie, oeie and eotie enable bits respectively in sien. the interrupt request is generated each time an enabled source flag is set, and the glo - bal sio interrupt enable bit is set (es in ien0 register). ti sint.0 eoti sint.5 gbit1:0 scon.1:0 brg clock txd tx shift reg ctsen scon.3 fifo & flow controller sbuf tx 1-byte fifo cts character handler
219 AT85C51SND3bx 7632a?mp3?03/06 figure 113. sio controller interrupt system registers reset value = 0000 0000b peie sien.3 tie sien.1 sio interrupt ri sint.0 feie sien.2 es ien0.4 rie sien.0 pei sint.3 oeie sien.4 ti sint.1 oei sint.4 fei sint.2 request eotie sien.5 eoti sint.5 table 242. scon register scon (0.91h) ? sio control register 7 6 5 4 3 2 1 0 sioen pmod1 pmod0 pben stop dlen gbit1 gbit0 bit number bit mnemonic description 7 sioen sio enable bit set to enable the serial input/output port. clear to disable the serial input/output port. 6-5 pmod1:0 parity mode bits refer to table 237 for information on parity mode 4 pben parity bit enable bit set to enable parity generation according to pmod1:0 bits. clear to disable parity generation. 3 stop stop bit number set to enable generation of 2 stop bits. clear to enable generation of 1 stop bit. 2 dlen data length bit set to enable generation of 7 data bits. clear to enable generation of 8 data bits. 1-0 gbit1:0 guard bit number number of guard bits (from 0 to 3) transmitted after the last stop bit in transmission mode.
220 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 0000b table 243. sfcon register sfcon (0.95h) ? sio flow control register 7 6 5 4 3 2 1 0 ovrsf3 ovrsf2 ovrsf1 ovrsf0 ctsen rtsen rtsth1 rtsth0 bit number bit mnemonic description 7-4 ovrsf3:0 over sampling factor bits number of time a data bit is sampled for level determination. oversampling factor = ovrsf3:0 + 1. 3 ctsen clear to send enable bit set to enable transmission hardware flow control using cts signal. clear to disable transmission hardware flow control. 2 rtsen request to send enable bit set to enable reception hardware flow control using rts signal. clear to disable reception hardware flow control. 1-0 rtsth1:0 request to send assertion threshold refer to table 241 for information on threshold values. table 244. sint register sint (1.a8h) ? sio interrupt source register 7 6 5 4 3 2 1 0 - - eoti oei pei fei ti ri bit number bit mnemonic description 7 - reserved the value read from this bit is always 0. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 eoti end of transmission interrupt flag set by hardware when both tx fifo and tx shift register are empty: actual end of transmission. cleared by hardware when the tx fifo or tx shift register are not empty. 4 oei overrun reception error interrupt flag set by hardware when a character is received while the rx shift register is full (rx fifo full). clear by software to acknowledge interrupt. 3 pei parity reception error interrupt flag set by hardware when a parity error occurs in a received character. clear by software to acknowledge interrupt. 2 fei framing reception error interrupt flag set by hardware when a framing error occurs in a received character. clear by software to acknowledge interrupt.
221 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0x10 0010b reset value = 0000 0000b 1 ti transmission interrupt flag set by hardware when the tx fifo is not full: a character can be loaded through sbuf. cleared by hardware when the tx fifo becomes full: no more character can be loaded. 0 ri reception interrupt flag set by hardware when the rx fifo is not empty: character ready to be read through sbuf. cleared by hardware when the rx fifo becomes empty: no more character to be read. table 245. sien register sien (1.a9h) ? sio interrupt enable register 7 6 5 4 3 2 1 0 - - eotie oeie peie feie tie rie bit number bit mnemonic description 7-6 - reserved the value read from these bits is always 0. do not set these bits. 5 eotie end of transmission interrupt enable bit set to enable end of transmission interrupt generation. clear to disable end of transmission interrupt generation. 4 oeie overrun error interrupt enable bit set to enable overrun error interrupt generation. clear to disable overrun error interrupt generation. 3 peie parity error interrupt enable bit set to enable parity error interrupt generation. clear to disable parity error interrupt generation. 2 feie framing error interrupt enable bit set to enable framing error interrupt generation. clear to disable framing error interrupt generation. 1 tie transmission interrupt enable bit set to enable transmission interrupt generation. clear to disable transmission interrupt generation. 0 rie reception interrupt enable bit set to enable reception interrupt generation. clear to disable reception interrupt generation. bit number bit mnemonic description
222 AT85C51SND3bx 7632a?mp3?03/06 reset value = xxxx xxxx b reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b table 246. sbuf register sbuf (1.aah) ? sio data buffer register 7 6 5 4 3 2 1 0 siod7 siod6 siod5 siod4 siod3 siod2 siod1 siod0 bit number bit mnemonic description 7-0 siod7:0 8-bit data buffer. table 247. sbrg0 register sbrg0 (0.92h) ? sio baud rate generator register 0 7 6 5 4 3 2 1 0 cdiv7 cdiv6 cdiv5 cdiv4 cdiv3 cdiv2 cdiv1 cdiv0 bit number bit mnemonic description 7-0 cdiv7:0 baud rate generator 8-bit c divider. table 248. sbrg1 register sbrg1 (0.93h) ? sio baud rate generator register 1 7 6 5 4 3 2 1 0 adiv7 adiv6 adiv5 adiv4 adiv3 adiv2 adiv1 adiv0 bit number bit mnemonic description 7-0 adiv7:0 baud rate generator 8-bit a divider. table 249. sbrg2 register sbrg2 (0.94h) ? sio baud rate generator register 2 7 6 5 4 3 2 1 0 bdiv7 bdiv6 bdiv5 bdiv4 bdiv3 bdiv2 bdiv1 bdiv0 bit number bit mnemonic description 7-0 bdiv7:0 baud rate generator 8-bit b divider.
223 AT85C51SND3bx 7632a?mp3?03/06 serial peripheral interface the AT85C51SND3bx implement a synchronous peripheral interface (spi) allowing full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus . features of the spi module include the following: ? full-duplex, three-wire synchronous transfers ? master or slave operation ? programmable master clock rates in master mode ? serial clock with programmable polarity and phase ? master mode fault error flag with mcu interrupt capability figure 114 shows a spi bus configuration using the AT85C51SND3bx as master con - nected to slave peripherals while figure 115 shows a spi bus configuration using the AT85C51SND3bx as slave of an other master. the bus is made of three wires connecting all the devices together: ? master output slave input (mosi): it is used to transfer data in series from the master to a slave. it is driven by the master. ? master input slave output (miso): it is used to transfer data in series from a slave to the master. it is driven by the selected slave. ? serial clock (sck): it is used to synchronize the data transmission both in and out the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. each slave peripheral is selected by one slave select pin ( ss ). if there is only one slave, it may be continuously selected with ss tied to a low level. otherwise, the AT85C51SND3bx may select each device by software through port pins (pn.x). special care should be taken not to select 2 slaves at the same time to avoid bus conflicts. figure 114. typical master spi bus configuration dataflash 1 ss so si sck dataflash 2 ss so si sck lcd controller ss so si sck AT85C51SND3b master miso mosi sck pn.z pn.y pn.x
224 AT85C51SND3bx 7632a?mp3?03/06 figure 115. typical slave spi bus configuration description the spi controller interfaces with the c51 core through three special function registers: spcon, the spi control register (see table 251 ); spscr, the spi status and control register (see table 252 ); and spdat, the spi data register (see table 253 ). data flow transfer can be fully handled by the c51 by writing and reading spdat or par - tially by the c51 and the dfc. the spi controller implements only one dfc channel, meaning only reception flow or transmission flow can be handled by the dfc at a time. the figure 116 summarizes the different data flow configuration allowed. figure 116. spi data flow configurations master mode the spi operates in master mode when the mstr bit in spcon is set. note: the spi module should be configured as a master before it is enabled (spen set). in a system, the master spi should be configured before the slave spi device. figure 117 shows the spi block diagram in master mode. only a master spi module can initiate transmissions. master slave 1 ss miso mosi sck ssn ss1 ss0 so si sck slave 2 ss so si sck AT85C51SND3b slave ss miso mosi sck dfc spi per x in out cpu spi in out cpu dfc spi in out dfc cpu per x per x ? data flow is fully handled by the cpu. ? peripheral x is configured as source and spi as destination of a dfc channel. cpu is still able to read incoming data (usually status) at its own rate. ? peripheral x is configured as destination and spi as source of a dfc channel. cpu is still able to output data (usually status) at its own rate.
225 AT85C51SND3bx 7632a?mp3?03/06 the transmission begins by writing to spdat through cpu or dfc. writing to spdat writes to an intermediate register which is automatically loaded to the shift register if no transmission is in progress. reading spdat through cpu or dfc reads an intermedi - ate register updated at the end of each transfer. the byte begins shifting out on the mosi pin under the control of the bit rate generator. this generator also controls the shift register of the slave peripheral through the sck output pin. as the byte shifts out, another byte shifts in from the slave peripheral on the miso pin. the byte is transmitted most significant bit (msb) first when uartm bit in spcr is cleared or least significant bit (lsb) first when uartm bit in spcr is set. the end of transfer is signaled by spif being set. in case spi is the source of a dfc channel (slave device data read), spdat is first loaded with a dummy byte ( ffh value) to initiate the transfer. then transfer continues by transmitting the shift register content which is the last data received. when the AT85C51SND3bx is the only master on the bus, it can be useful not to use ss pin and get it back to i/o functionality. this is achieved by setting ssdis bit in spcon. figure 117. spi master mode block diagram note: mstr bit in spcon is set to select master mode. slave mode the spi operates in slave mode when the mstr bit in spcon is cleared and data has been loaded in spdat. note: the spi module should be configured as a slave before it is enabled (spen set). figure 118 shows the spi block diagram in slave mode. in slave mode, before a data transmission occurs, the ss pin of the slave spi must be asserted to low level. ss must remain low until the transmission of the byte is complete. in the slave spi module, data enters the shift register through the mosi pin under the control of the serial clock pro - vided by the master spi module on the sck input pin. when the master starts a transmission, the data in the shift register begins shifting out on the miso pin. the end of transfer is signaled by spif being set. uartm spscr.2 spr2:0 spcon per clock spen spcon.6 8-bit shift register bit rate mosi/p3.1 miso/p3.0 sck/p3.2 cpol spcon.3 cpha spcon.2 iq cpu or dfc bus spdat rd control modf spscr.4 ss /p3.3 ssdis spcon.5 ovr spscr.6 spif spscr.7 generator and clock logic spdat wr spte spscr.3
226 AT85C51SND3bx 7632a?mp3?03/06 when the AT85C51SND3bx is the only slave on the bus, it can be useful not to use ss pin and get it back to i/o functionality. this is achieved by setting ssdis bit in spcon. this bit has no effect when cpha is cleared (see section "ss management", page 227 ). figure 118. spi slave mode block diagram note: mstr bit in spcon is cleared to select slave mode. bit rate in master mode, the bit rate can be selected from seven predefined bit rates using the spr2, spr1 and spr0 control bits in spcon according to table 250 . these bit rates are derived from the peripheral clock (f per ) issued from the clock controller block as detailed in section "clock controller", page 27 . in slave mode, the maximum baud rate allowed on the sck input is limited to fosc 4. table 250. serial bit rates notes: 1. these frequencies are achieved in x1 mode, f per = f osc 2. 2. these frequencies are achieved in x2 mode, f per = f osc . uartm spscr.2 8-bit shift register miso/p3.0 mosi/p3.1 cpol spcon.3 cpha spcon.2 iq cpu or dfc bus spdat rd control modf spscr.4 ss /p3.3 ssdis spcon.5 ovr spscr.6 spif spscr.7 and clock logic spdat wr spte spscr.3 sck/p3.2 spr2 spr1 spr0 bit rate (khz) vs f per (mhz) f per divider 6 (1) 8 (1) 10 (1) 12 (1)(2) 16 (2) 20 (2) 24 (2) 0 0 0 3000 4000 5000 6000 8000 10000 12000 2 0 0 1 1500 2000 2500 3000 4000 5000 6000 4 0 1 0 750 1000 1250 1500 2000 2500 3000 8 0 1 1 375 500 625 750 1000 1250 1500 16 1 0 0 187.5 250 312.5 375 500 625 750 32 1 0 1 93.75 125 156.25 187.5 250 312.5 375 64 1 1 0 46.875 62.5 78.125 93.75 125 156.25 187.5 128 1 1 1 - - - - - - - reserved
227 AT85C51SND3bx 7632a?mp3?03/06 data transfer the clock polarity bit (cpol in spcon) defines the default sck line level in idle state (1) while the clock phase bit (cpha in spcon) defines the edges on which the input data are sampled and the edges on which the output data are shifted (see figure 119 and figure 120 ). for simplicity, figure 119 and figure 120 depict the spi waveforms in idealized form and do not provide precise timing information. for timing parameters refer to the section ?ac characteristics?, page 246 . note: 1. when the peripheral is disabled (spen = 0), default sck line is high level. figure 119. data transmission format (cpha = 0, uartm = 0) figure 120. data transmission format (cpha = 1, uartm = 0) ss management figure 119 shows a spi transmission with cpha = 0, where the first sck edge is the msb capture point. therefore the slave starts to output its msb as soon as it is selected: ss asserted to low level. ss must then be de-asserted between each byte transmission (see figure 121 ). spdat must be loaded with a data before ss is asserted again. note: in master mode, spi transmission with cpha = 0 is not allowed in case of dfc transfer. 1 2 3 4 5 6 7 8 msb bit 1 lsb bit 2 bit 4 bit 3 bit 6 bit 5 bit 1 bit 2 bit 4 bit 3 bit 6 bit 5 msb lsb mosi (from master) miso (from slave) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number ss (to slave) capture point 1 2 3 4 5 6 7 8 msb bit 1 lsb bit 2 bit 4 bit 3 bit 6 bit 5 bit 1 bit 2 bit 4 bit 3 bit 6 bit 5 msb lsb mosi (from master) miso (from slave) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number ss (to slave) capture point
228 AT85C51SND3bx 7632a?mp3?03/06 figure 120 shows a spi transmission with cpha = 1, where the first sck edge is used by the slave as a start of transmission signal. therefore, ss may remain asserted between each byte transmission (see figure 121 ). this format may be preferred in sys - tems having only one master and only one slave driving the miso data line. figure 121. ss timing diagram queuing transmission for a spi configured in master or slave mode, a queued data byte must be transmit - ted/received immediately after the previous transmission has completed. when a transmission is in progress a new data can be queued and sent as soon as transmission has been completed. so it is possible to transmit bytes without latency, useful in some applications. the spte bit in spscr is set as long as the transmission buffer is free. it means that the user application can write spdat with the next data to be transmitted until the spte becomes cleared. figure 122 shows a queuing transmission in master mode. once the byte 1 is ready, it is immediately sent on the bus. meanwhile an other byte is prepared (and the spte is cleared), it will be sent at the end of the current transmission. the next data must be ready before the end of the current transmission. figure 122. queuing transmission in master mode in slave mode it is almost the same except it is the external master that starts the trans - mission. also, in slave mode, if no new data is ready, the last value received will be the next data byte transmitted. error conditions the following flags in spscr register signal the spi error conditions: ? modf signals a mode fault condition. ? ovr signals an overrun condition. mode fault in master mode modf is set to warn that there may be a multi-master conflict for system control. in this case, the spi controller is affected in the following ways: ? a spi receiver/error cpu interrupt request is generated ? the spen bit in spcon is cleared. this disables the spi ss (cpha = 1) ss (cpha = 0) si/so byte 1 byte 2 byte 3 msb b6 b5 b4 b3 b2 b1 lsb mosi sck msb b6 b5 b4 b3 b2 b1 lsb byte 1 under transmission msb b6 b5 b4 b3 b2 b1 lsb msb b6 b5 b4 b3 b2 b1 lsb miso data byte 1 byte 2 byte 3 spte byte 2 under transmission
229 AT85C51SND3bx 7632a?mp3?03/06 ? the mstr bit in spcon is cleared clearing the modf bit is accomplished by reading spscr with modf bit set, followed by a write to spcon. spi controller may be re-enabled (spen = 1) after the modf bit is cleared. figure 123. mode fault conditions in master mode (cpha = 1 / cpol = 0) note: when ss is disabled (ssdis set) it is not possible to detect a modf error in master mode because the spi is internally unselected and the ss pin is a general purpose i/o. mode fault in slave mode modf error is detected when ss goes high during a transmission. a transmission begins when ss goes low and ends once the incoming sck goes back to its idle level following the shift of the eighth data bit. a modf error occurs if a slave is selected ( ss is low) and later unselected ( ss is high) even if no sck is sent to that slave. at any time, a ?1? on the ss pin of a slave spi puts the miso pin in a high impedance state and internal state counter is cleared. also, the slave spi ignores all incoming sck clocks, even if it was already in the middle of a transmission. a new transmission will be performed as soon as ss pin returns low. figure 124. mode fault conditions in slave mode note: when ss is disabled (ssdis set) it is not possible to detect a modf error in slave mode because the spi is internally selected. also the ss pin becomes a general purpose i/o. sck (from master) ss (master) 1 2 3 sck cycle number 0 0 ss (slave) modf detected b6 msb b6 msb 0 z 1 0 z 1 0 z 1 0 z 1 0 z 1 0 0 z 1 spi enable modf detected mosi (from master) miso (from slave) b5 sck (from master) 1 2 3 sck cycle number 0 ss (slave) modf detected b6 msb b6 msb 0 z 1 0 z 1 0 z 1 0 z 1 0 modf detected mosi (from master) miso (from slave) msb b5 b4 4
230 AT85C51SND3bx 7632a?mp3?03/06 overrun condition this error means that the speed is not adapted for the running application. an overrun condition occurs when a byte has been received whereas the previous one has not been read by the application yet. the last byte (which generate the overrun error) does not overwrite the unread data so that it can still be read. therefore, an overrun error always indicates the loss of data. interrupt the spi handles 3 interrupt sources that are the ?end of transfer?, the ?mode fault? and the ?transmit register empty? flags. as shown in figure 125 , these flags are combined together to appear as a single inter - rupt source for the c51 core. the spif flag is set at the end of an 8-bit shift in and out and is cleared by reading spscr and then reading from or writing to spdat. the modf flag is set in case of mode fault error and is cleared by reading spscr and then writing to spcon. the spte flag is set when the transmit register is empty and ready to receive new data. when spte interrupt source is enabled, spif flag does not generate any interrupt. the spi interrupt is enabled by setting espi bit in ien1 register. this assumes inter - rupts are globally enabled by setting ea bit in ien0 register. figure 125. spi interrupt system registers espi ien1.3 spteie spscr.1 spi controller interrupt request spif spscr.7 modf spscr.4 spte spscr.3 modfie spscr.0 table 251. spcon register spcon (1:91h) ? spi control register 7 6 5 4 3 2 1 0 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic description 7 spr2 spi rate bit 2 refer to ta b l e 250 for bit rate description. 6 spen spi enable bit set to enable the spi interface. clear to disable the spi interface. 5 ssdis slave select input disable bit set to disable ss in both master and slave modes. in slave mode this bit has no effect if cpha = 0. clear to enable ss in both master and slave modes.
231 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0001 0100b 4 mstr master mode select set to select the master mode. clear to select the slave mode. 3 cpol spi clock polarity bit set to have the clock output set to high level in idle state. clear to have the clock output set to low level in idle state. 2 cpha spi clock phase bit set to have the data sampled when the clock returns to idle state (see cpol). clear to have the data sampled when the clock leaves the idle state (see cpol). 1-0 spr1:0 spi rate bits 0 and 1 refer to ta b l e 250 for bit rate description. table 252. spscr register spscr (1.92h) ? spi status and control register 7 6 5 4 3 2 1 0 spif - ovr modf spte uartm spteie modfie bit number bit mnemonic description 7 spif spi interrupt flag set by hardware when an 8-bit shift is completed. cleared by hardware to indicate data transfer is in progress or has been acknowledged by a clearing sequence: reading or writing spdat after reading spscr. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 ovr overrun error flag set by hardware when a byte is received whereas spif is set (the previous received data is not overwritten). cleared by hardware when reading spscr. 4 modf mode fault interrupt flag set by hardware to indicate that the ss pin is in inappropriate logic level. cleared by hardware when reading spscr when modf error occurred: - in slave mode: spi interface ignores all transmitted data while ss remains high. a new transmission is perform as soon as ss returns low. - in master mode: spi interface is disabled (spen=0, see description for spen bit in spcon register). 3 spte serial peripheral transmit register empty interrupt flag set by hardware when transmit register is empty (if needed, spdat can be loaded with another data). cleared by hardware when transmit register is full (no more data should be loaded in spdat). 2 uartm serial peripheral uart mode set to select uart mode: data is transmitted lsb first. clear to select spi mode: data is transmitted msb first. bit number bit mnemonic description
232 AT85C51SND3bx 7632a?mp3?03/06 reset value = 0000 1000b reset value = xxxx xxxxb 1 spteie spte interrupt enable bit set to enable spte interrupt generation. clear to disable spte interrupt generation. 0 modfie modf interrupt enable bit set and cleared by software: - set to enable modf interrupt generation - clear to disable modf interrupt generation table 253. spdat register spdat (1:93h) ? synchronous serial data register 7 6 5 4 3 2 1 0 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 bit number bit mnemonic description 7-0 spd7:0 synchronous serial data. bit number bit mnemonic description
233 AT85C51SND3bx 7632a?mp3?03/06 display interface the AT85C51SND3bx implement a display interface allowing glueless direct interfacing (thanks to its highly configurable capability) to almost all of the lcd controllers found in either graphic or text lcd display. these lcd controllers interface is from either 6800 or 8080 compatible type with some variant in the implementation. the display interfaces to the c51 core through the following special function registers: lcdcon0, lcdcon1, the lcd control registers (see table 255 and table 256 ); lcd - sta, the lcd status register (see table 257 ); lcdbum, the lcd busy mask register (see table 258 ); and lcddat, the lcd data register (see table 259 ). as shown in figure 126 , the display interface is divided in two major blocks: the access cycle generator which generates read or write cycles to the lcd controller, and the busy check processor which enables automatic busy checking after any read or write cycles. figure 126. display interface block diagram configuration interface enable setting lcen bit in lcdcon1 enables the display interface. when this bit is cleared, all signals to the controller are switch back to i/o port alternate function. thus after reset, all signals are set to high level. interface selection the display interface is programmed in 6800 type or 8080 type by setting or clearing the lcifs bit lcdcon0. table 254 shows the pin configuration depending on the interface selected. table 254. pin configuration vs. lcd controller interface type (6800/8080) slw1:0 lcdcon1.7:6 lcrs lcdcon1.0 lcrd lcdcon1.1 rscmd lcdcon1.5 lcen lcdcon1.2 bu7:0 lcdbum buinv lcdcon0.7 busy check processor osc clock lwr /lrw lrd /lde la0/lrs lcs ld7:0 lcycw lcdcon1.4 adsuh1:0 lcdcon0.5:4 lcbusy lcdcsta accw3:0 lcdcon0.3:0 access cycle generator lcifs lcdcon0.6 lcyct lcdcon1.3 pin name 8080 type controller 6800 type controller lwr /lrw wr rw lrd /lde rd e la0/lrs a0 rs lcs cs cs ld7:0 d7:0 d7:0
234 AT85C51SND3bx 7632a?mp3?03/06 access cycles the AT85C51SND3bx enables connection of lcd controller with normalized 6800 and 8080 interface as shown in figure 127 and figure 128 , but also enables connection of lcd controller with non normalized 6800 and 8080 interface as shown in figure 129 and figure 130 . this is achieved by setting or clearing cyct bit in lcdcon1 for selecting non normal - ized or normalized access type. figure 127. 6800 normalized type access cycle figure 128. 8080 normalized type access cycle figure 129. 6800 special type access cycle figure 130. 8080 special type access cycle timings configuration as detailed in figure 131 , access cycle timing can be configured to comply with the lcd controller specification. these timing parameters are: ? address set-up time ? access width time ? address hold time ? sleep wait time address set-up and hold time the address set-up and hold time can be programmed by adsuh1:0 bits in lcdcon0 from 1 oscillator clock period up to 4 oscillator clock periods. these timing are not disso - ciated and must be programmed to the highest time value of the set-up and hold time parameters. access width time the access width time can be programmed by accw3:0 bits in lcdcon0 from 1 oscil - lator clock period up to 16 oscillator clock period. cs , rw, rs e adsuh adsuh accw cs , a0 rd , wr adsuh adsuh accw e, rw, rs cs adsuh adsuh accw a0 cs , rd , wr adsuh adsuh accw
235 AT85C51SND3bx 7632a?mp3?03/06 sleep wait time the sleep wait time is the time between two consecutive access cycle. it can be pro - grammed by slw1:0 bits in lcdcon1 from 1 oscillator clock period up to 4 oscillator clock periods full access cycle time the full access cycle time can be computed by adding the address set-up time, the access width time, the address hold time and the sleep wait time. however, some lcd controller may require that the inactive state of the selection signal being equal to the access width time. in su ch case, lcycw bit in lcdcon1 must be set. figure 131. full access cycle timing automatic busy process an automatic busy check process can be enabled after any read or write access to the lcd controller to verify this one is ready to execute next instruction. busy check configuration uses buinv bit in lcdcon0, bum7:0 data in lcdbum and rscmd bit in lcdcon1. rscmd is used to program the address of the status register (l or h depending on the lcd controller) during the status read cycle. the busy process performs reads of the lcd controller status register until all relevant busy bits are deasserted (i.e. controller ready). relevant bits are selected by the bum7:0 bits set. and busy asserted level is programmed by buinv, set this bit when busy bit(s) are asserted low, clear it otherwise. when lcdbum is reset (i.e. all bits cleared), no busy check is performed. busy report the busy state report is done by the lcbusy flag in lcdsta. lcbusy is set at the beginning of any read or write cycles and cleared at the end of any access cycle (after the sleep wait time) when the automatic busy check process is disabled or at the end of the first lcd controller ready status read cycle (after the sleep wait time) when the auto - matic busy check process is enabled. lcbusy flag must be checked before performing any read or write cycle to the lcd controller. read / write operation lcd controllers have two registers, the display data register and instruction/status regis - ter. to determine which register will be accessed, lcrs bit in lcdcon1 must be configured according to the lcd controller. write access while the display interface is enabled, writing a data to lcddat launches a write cycle to the lcd controller according to the programmed configuration. read access while the display interface is enabled, setting lcrd bit in lcdcon1 launches a read cycle to the lcd controller according to the programmed configuration. at the end of the read cycle, including busy time, data can be retrieved by reading lcdat. reading lcdat automatically relaunches a new read cycle to the lcd controller allowing contin - uous read of data. address enable adsuh accw adsuh slw adsuh accw (lcycw = 1) select
236 AT85C51SND3bx 7632a?mp3?03/06 registers reset value= 0000 0000b table 255. lcdcon0 register lcdcon0 (1.96h) ? lcd control register 0 7 6 5 4 3 2 1 0 buinv lcifs adsuh1 adsuh0 accw3 accw2 accw1 accw0 bit number bit mnemonic description 7 buinv busy invert active set to check busy bits selected in lcdbum as active low. clear to check busy bits selected in lcdbum as active high. 6 lcifs interface select bit set to select 6800 interface type. clear to select 8080 interface type. 5-4 adsuh1:0 address setup/hold address setup and hold length in clock periods (from 1 to 4 clock periods). 3-0 accw3:0 access cycle width access width in clock periods (from 1 to 16 clock periods). in 8080 mode, corresponds to wr or rd low state. in 6800 mode, corresponds to e high state. table 256. lcdcon1 register lcdcon1 (1.8eh) ? lcd control register 1 7 6 5 4 3 2 1 0 slw1 slw0 rscmd lcycw lcyct lcen lcrd lcrs bit number bit mnemonic description 7-6 slw1:0 sleep wait states busy check process enabled number of wait states between a read or write access and a busy check process (from 1 to 4 clock periods). busy check process disabled number of wait states between two read or write accesses (from 1 to 4 clock periods). 5 rscmd rs command/status set to output high level on la0/lrs pin during busy check process. clear to output low level on la0/lrs pin during busy check process. this value depends on the lcd controller. 4 lcycw deassertion cycle width set to program e or rd / wr signals deassertion time to the number of clock set in accw3:0 bits. clear to let e or rd / wr signals deassertion time to the number of clock set in adsuh1:0 + slw1:0.
237 AT85C51SND3bx 7632a?mp3?03/06 reset value= 0000 0000b reset value= 0000 0000b reset value= 0000 0000b 3 lcyct cycle type selection set to select non normalized access cycles (6800 or 8080 interface). clear to select normalized access cycles (6800 or 8080 interface). 2 lcen lcd interface enable set to enable the lcd interface. clear to disable the lcd interface. 1 lcrd lcd read command set to initiate a read data or status register from lcd controller. cleared by hardware at the end of read. 0 lcrs lcd register select set to output high level on la0/lrs pin during next read or write access. clear to output low level on la0/lrs pin during next read or write access. this value depends on the lcd controller. table 257. lcdsta register lcdsta (1.8fh) ? lcd status register 7 6 5 4 3 2 1 0 - - - - - - - lcbusy bit number bit mnemonic description 7:1 - reserved the value read from these bits is always 0. do not set these bits. 0 lcbusy busy flag set by hardware during any access to the lcd controller and while lcd controller is busy if busy check process is enabled. table 258. lcdbum register lcdbum (1.8dh) ? lcd busy mask register 7 6 5 4 3 2 1 0 bum7 bum6 bum5 bum4 bum3 bum2 bum1 bum0 bit number bit mnemonic description 7:0 bum7:0 busy mask set bits to be checked during the busy check process and thus enable the busy check process. clear all bits to disable the busy check process. bit number bit mnemonic description
238 AT85C51SND3bx 7632a?mp3?03/06 reset value= 0000 0000b table 259. lcddat register lcddat (1.97h) ? lcd data register 7 6 5 4 3 2 1 0 ld7 ld6 ld5 ld4 ld3 ld2 ld1 ld0 bit number bit mnemonic description 7:0 ld7:0 lcd data byte reading a data automatically initiates a new read cycle to the lcd controller.
239 AT85C51SND3bx 7632a?mp3?03/06 keyboard interface the AT85C51SND3bx implement a keyboard interface allowing the connection of a 4 x n matrix keyboard. it is based on 4 inputs with programmable interrupt capability on both high or low level. these inputs are available as alternate function of p1.3:0 and allow exit from idle and power down modes. description the keyboard interfaces with the c51 core through 2 special function registers: kbcon, the keyboard control register (see table 260 ); and kbsta, the keyboard control and status register (see table 261 ). the keyboard inputs are considered as 4 independent interrupt sources sharing the same interrupt vector. an interrupt enable bit (ekb in ien1 register) allows global enable or disable of the keyboard interrupt (see figure 132 ). as detailed in figure 133 each keyboard input has the capability to detect a programmable level according to kinl3:0 bit value in kbcon register. level detection is then reported in interrupt flags kinf3:0 in kbsta register. a keyboard interrupt is requested each time one of the four flags is set, i.e. the input level matches the programmed one. each of these four flags can be masked by soft - ware using kinm3:0 bits in kbcon register and is cleared by reading kbsta register. this structure allows keyboard arrangement from 1 by n to 4 by n matrix and allows usage of kin inputs for any other purposes. figure 132. keyboard interface block diagram figure 133. keyboard input circuitry power reduction modes kin3:0 inputs allow exit from idle and power-down modes as detailed in section ?power reduction mode?, page 20 . to enable power-down mode exit, kpde bit in kbsta reg - ister must be set. due to the asynchronous keypad detection in power down mode (all clocks are stopped), exit may happen on parasitic key press. in this case, no key is detected and software returns to power down again. kdcpl kbsta.5 kin3 keyboard interfac e interrupt request ekb ien1.1 kin2 kin1 kin0 input circuitry input circuitry input circuitry input circuitry dcpwr kdcpe kbsta.6 kinm3:0 kbcon.3:0 kinf3:0 kbsta.3:0 kinl3:0 kbcon.7:4 0 1
240 AT85C51SND3bx 7632a?mp3?03/06 registers table 260. kbcon register kbcon (0.a3h) ? keyboard control register reset value = 0000 1111b table 261. kbsta register kbsta (0.a4h) ? keyboard control and status register reset value = 0010 0000b 7 6 5 4 3 2 1 0 kinl3 kinl2 kinl1 kinl0 kinm3 kinm2 kinm1 kinm0 bit number bit mnemonic description 7-4 kinl3:0 keyboard input level bit set to enable a high level detection on the respective kin3:0 input. clear to enable a low level detection on the respective kin3:0 input. 3-0 kinm3:0 keyboard input mask bit set to prevent the respective kinf3:0 flag from generating a keyboard interrupt. clear to allow the respective kinf3:0 flag to generate a keyboard interrupt. 7 6 5 4 3 2 1 0 kpde kdcpe kdcpl - kinf3 kinf2 kinf1 kinf0 bit number bit mnemonic description 7 kpde keyboard power down enable bit set to enable exit of power down mode by the keyboard interrupt. clear to disable exit of power down mode by the keyboard interrupt. 6 kdcpe keyboard dcpwr pin enable set to connect dcpwr pin on kin0 input. clear to isolate dcpwr pin from kin0 input. 5 kdcpl keyboard dcpwr pin line set by hardware and represent the level on dcpwr input. 4 - reserved the value read from this bit is always 0. do not set this bit. 3-0 kinf3:0 keyboard input interrupt flag set by hardware when the respective kin3:0 input detects a programmed level. cleared when reading kbsta.
4 AT85C51SND3bx 7632a?mp3?03/06 electrical characteristics absolute maximum rating dc characteristics digital logic table 257. digital dc characteristics iov dd = 1.65 to 3.6 v; t a = -40 to +85c notes: 1. typical values are obtained at t a = 25 c. they are not tested and there is no guaran- tee on these values. storage temperature ......................................... -65 to +150c voltage on any other pin to v ss .................................... -0.3 to +4.0 v i ol per i/o pin ................................................................. 5 ma power dissipation ............................................................. 1 w operating conditions ambient temperature under bias........................ -40 to +85c v dd ................................................................................................................... tbd v *notice: stressing the device beyond the ?absolute maxi - mum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. symbol parameter min typ (1) max units test conditions v il input low voltage -0.5 0.25iov dd v v ih1 input high voltage (except x1) 0.65iov dd iov dd +0.5 v v ih2 input high voltage ( x1) 0.7iov dd iov dd +0.5 v v ol output low voltage 0.4 v i ol = 3 ma v oh1 output high voltage (p0, p1, p2, p3, p4, p5) iov dd -0.7 v i oh = -30 a v oh2 output high voltage (nfd7:0, nfale, nfcle, nfre , nfwe , nfce3:0 , ld7:0, sdcmd, sdlck, sddat3:0, rxd, txd, miso, mosi, rts , lcs , la0/lrs, lrd /lde, lwr /lrw, scs , srd , swr , sa0, oclk, dclk, ddat, dsel) iov dd -0.7 v i oh = -3 ma i il logical 0 input current (p0, p1, p2, p3, p4, p5) -50 a v in = 0.4 v i li input leakage current (nfd7:0, nfale, nfcle, nfre , nfwe , nfce0 ) 10 a 0 < v in < v dd i tl logical 1 to 0 transition current (p0, p1, p2, p3, p4 and p5) -650 a v in = 1.0 v v in = 2.0 v r rst rst pull-up resistor 10 16 21 k c io pin capacitance 10 pf t a = 25 c
5 AT85C51SND3bx 7632a?mp3?03/06 oscillator & crystal schematic figure 134. crystal connection note: for operation with most standard crystals, no external components are needed on x1 and x2. it may be necessary to add external capacitors on x1 and x2 to ground in spe - cial cases (max 10 pf). parameters table 258. oscillator & crystal characteristics v dd = 1.65 to 3.6 v; t a = -40 to +85c notes: 1. authorized crystal frequencies are 12, 16, 20 and 24 mhz 2. authorised input frequencies are 12, 13, 16, 19.2, 19.5, 20, 24 and 26mhz dc to dc convertor schematic figure 135. battery dc-dc connection notes: 1. mandatory connection if dc-dc is used. 2. depending on power supply scheme, c dc1 may replace c lv capacitor (see figure 136 ). apvss x1 x2 q c1 c2 symbol parameter min typ max unit c x1 internal capacitance (x1 - vss) 10 pf c x2 internal capacitance (x2 - vss) 10 pf c l equivalent load capacitance (x1 - x2) 5 pf dl drive level 50 w f crystal frequency (1) 12 24 mhz rs crystal series resistance 40 cs crystal shunt capacitance 6 pf lvdd bvdd bvss battery l dc dcli c dc1 (2) vss rlvdd cvss c dc2 (1)
6 AT85C51SND3bx 7632a?mp3?03/06 parameters table 259. dc-dc filter characteristics t a = -40 to +85c table 260. dc-dc power characteristics v bat = 0.9 to 3.6 v; t a = -40 to +85c regulators schematic figure 136. regulator connection note: depending on power supply scheme, c lv may replace c dc1 capacitor (see figure 135 ). parameters table 261. regulator filter characteristics t a = -40 to +85 c table 262. high voltage regulator power characteristics uv cc = 4.4 to 5.5 v; t a = -40 to +85c symbol parameter min typ max unit l dc dc-dc inductance 10 h c dc1 low esr decoupling capacitor 20 f c dc2 low esr decoupling capacitor 100 nf symbol parameter min typ max unit test conditions v bat dc-dc input voltage 0.9 3.6 v i dc = 40 ma v dc dc-dc output voltage 1.6 1.75 1.9 v i dc = 40 ma i dc dc-dc output current 40 ma v bat = 1.0 v h max maximum efficiency 92 % v bat = 1.5 v f switch switching frequency 0.5 1.5 3 mhz r dcp dcpwr input pull-up resistor 30 k hvdd c hv vss rlvdd c lv ( * ) vss symbol parameter min typ max unit c hv decoupling capacitor 10 f c lv decoupling capacitor 20 f symbol parameter min typ max unit test conditions v hv high voltage regulator output voltage 3.1 3.3 3.5 v i dc = 50 ma i hv high voltage regulator output current 50 ma
7 AT85C51SND3bx 7632a?mp3?03/06 table 263. low voltage regulator power characteristics hv dd = 3 to 3.6 v; t a = -40 to +85c usb schematic figure 137. usb connection parameters table 264. usb component characteristics t a = -40 to +85 c audio codec schematic figure 138. audio codec connection symbol parameter min typ max unit test conditions v lv low voltage regulator output voltage 1.7 1.8 1.9 v i dc = 50 ma i lv low voltage regulator output current 50 ma dph dmh vbus gnd d+ d- r uft uvcc dpf dmf r uft ubias c ub r ub uvss vss uid id symbol parameter min typ max unit r uft usb full speed termination resistor 39 r ub usb bias filter resistor 6810 c ub usb bias filter capacitor 10 pf avss2 outr outl c out c out linl linr c inl c inl avcm avs s1 c vcm aref c aref avs s1 micin c inm micbias c mb av ss 1
8 AT85C51SND3bx 7632a?mp3?03/06 parameters table 265. audio codec components characteristics t a = -40 to +85c notes: 1. value in low impedance mode (headphone mode when aodrv = 1) 2. value in high impedance mode (line out mode when aodrv = 0) mmc controller schematic figure 139. mmc connection parameters table 266. mmc components characteristics t a = -40 to +85c symbol parameter min typ max unit c out outr/outl dc-decoupling capacitor 100 (1) 0.1 (2) f c inl linr/linl dc-decoupling capacitor 1 f c inm micin dc-decoupling capacitor 1 f c vcm avcm filter capacitor 100 nf c aref aref filter capacitor 1 f c mb micbias filter capacitor 10 nf r cmd iovdd sddat0 sdcmd r dat symbol parameter min typ max unit r cmd mmc/sd command line pull-up resistor 100 k r dat mmc/sd data line pull-up resistor 10 k
9 AT85C51SND3bx 7632a?mp3?03/06 ac characteristics nfc interface definition of symbols table 1. nfc interface timing symbol definitions timings table 267. nfc interface ac timings v dd = 1.65 to 3.6 v; t a = -40 to +85c, cl 40pf (4 nf) note: 1. refer to trs bit in nfcon register. signals conditions d nfd7:0 in h high o nfd7:0 out l low r nfre v valid w nfwe x no longer valid e nfcen z floating a nfale c nfcle symbol parameter min max unit t elwh nfcen write setup time 3t nfc -?? ns t wheh nfcen write hold time 1t nfc -?? ns t chwh nfcle setup time 3t nfc -?? ns t whcl nfcle hold time 1t nfc -?? ns t ahwh nfale setup time 3t nfc -?? ns t whal nfale hold time 1t nfc -?? ns t wlwh nfwe pulse width 2t nfc -?? ns t ovwh data setup time 2t nfc -?? ns t whox data hold time 1t nfc -?? ns t eldv nfcen access time ?? ns t rlrh nfre pulse width 2t nfc -?? 3t nfc -?? ns (1) t rldv nfre access time ?? ns t rhdx data hold time ?? ns t rhdz data float after nfre high ?? ns t ehdz data float after nfcen high ?? ns
10 AT85C51SND3bx 7632a?mp3?03/06 waveforms figure 140. nfc command latch cycle waveforms figure 141. nfc address latch cycle waveforms figure 142. nfc read cycle waveforms t wlwh nfd7:0 nfale nfcle nfcen command nfwe t elwh t chwh t wheh t whcl t whox t ovwh t wlwh nfd7:0 nfale nfcle nfcen col add nfwe t elwh t ahwh t wheh t whal t whox t ovwh t rlrh nfd7:0 nfale nfcle nfcen data nfre t eldv t ehdz t rhdx t rhdz t rldv
11 AT85C51SND3bx 7632a?mp3?03/06 figure 143. nfc write cycle waveforms mmc interface definition of symbols table 268. mmc interface timing symbol definitions timings table 269. mmc interface ac timings v dd = 1.65 to 3.6 v; t a = -40 to +85c, cl 40pf (4 cards) t wlwh nfd7:0 nfale nfcle nfcen data nfwe t elwh t wheh t whox t ovwh signals conditions c clock h high d data in l low o data out v valid x no longer valid symbol parameter min max unit t chch clock period 40 ns t chcx clock high time 10 ns t clcx clock low time 10 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t dvch input data valid to clock high 3 ns t chdx input data hold after clock high 3 ns t chox output data hold after clock high 5 ns t ovch output data valid to clock high 5 ns
12 AT85C51SND3bx 7632a?mp3?03/06 waveforms figure 144. mmc input-output waveforms lcd interface to be defined definition of symbols timings waveforms sio interface to be defined definition of symbols timings waveforms spi interface definition of symbols table 270. spi interface timing symbol definitions timings test conditions: capacitive load on all pins= 50 pf. t ivch mclk mdat input t chch t clcx t chcx t chcl t clch mcmd input t chix t ovch mdat output mcmd output t chox signals conditions c clock h high i data in l low o data out v valid x no longer valid z floating
13 AT85C51SND3bx 7632a?mp3?03/06 table 271. spi interface master ac timing v dd = 1.65 to 3.6 v; t a = -40 to +85c note: 1. value of this parameter depends on software. symbol parameter min max unit slave mode t chch clock period 2 t per t chcx clock high time 0.8 t per t clcx clock low time 0.8 t per t slch , t slcl ss low to clock edge 100 ns t ivcl , t ivch input data valid to clock edge 40 ns t clix , t chix input data hold after clock edge 40 ns t clov, t chov output data valid after clock edge 40 ns t clox , t chox output data hold time after clock edge 0 ns t clsh , t chsh ss high after clock edge 0 ns t slov ss low to output data valid 50 ns t shox output data hold after ss high 50 ns t shsl ss high to ss low (1) t ilih input rise time 2 s t ihil input fall time 2 s t oloh output rise time 100 ns t ohol output fall time 100 ns master mode t chch clock period 2 t per t chcx clock high time 0.8 t per t clcx clock low time 0.8 t per t ivcl , t ivch input data valid to clock edge 20 ns t clix , t chix input data hold after clock edge 20 ns t clov, t chov output data valid after clock edge 40 ns t clox , t chox output data hold time after clock edge 0 ns t ilih input data rise time 2 s t ihil input data fall time 2 s t oloh output data rise time 50 ns t ohol output data fall time 50 ns
14 AT85C51SND3bx 7632a?mp3?03/06 waveforms figure 145. spi slave waveforms (sscpha= 0) note: 1. not defined but generally the msb of the character which has just been received. figure 146. spi slave waveforms (sscpha= 1) note: 1. not defined but generally the lsb of the character which has just been received. t slcl t slch t chcl t clch mosi (input) sck (sscpol= 0) (input) ss (input) sck (sscpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t chcl t clch mosi (input) sck (sscpol= 0) (input) ss (input) sck (sscpol= 1) (input) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t clov t chov t clox t chox msb in bit 6 lsb in slave msb out slave lsb out bit 6 t slov (1) t shox t shsl t chsh t clsh t slcl t slch
15 AT85C51SND3bx 7632a?mp3?03/06 figure 147. spi master waveforms (sscpha= 0) note: ss handled by software using general purpose port pin. figure 148. spi master waveforms (sscpha= 1) note: ss handled by software using general purpose port pin. mosi (input) sck (sscpol= 0) (output) ss (output) sck (sscpol= 1) (output) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch mosi (input) sck (sscpol= 0) (output) ss (1) (output) sck (sscpol= 1) (output) miso (output) t chch t clcx t chcx t ivcl t clix t chix t ivch t chov t clov t chox t clox msb in bit 6 lsb in msb out port data lsb out port data bit 6 t chcl t clch
16 AT85C51SND3bx 7632a?mp3?03/06 audio dac interface definition of symbols table 272. audio dac interface timing symbol definitions timings table 273. audio interface ac timings v dd = 1.65 to 3.6 v; t a = -40 to +85c, cl 30pf note: 1. 32-bit format with fs= 48 khz. waveforms figure 149. audio interface waveforms external clock interface definition of symbols table 274. external clock timing symbol definitions signals conditions c clock h high o data out l low s data select v valid x no longer valid symbol parameter min max unit t chch clock period 325.5 (1) ns t chcx clock high time 30 ns t clcx clock low time 30 ns t clch clock rise time 10 ns t chcl clock fall time 10 ns t clsv clock low to select valid 10 ns t clov clock low to data valid 10 ns d clk t chch t clcx t chcx t clch t chcl dsel d dat right left t clsv t clov signals conditions c clock h high l low x no longer valid
17 AT85C51SND3bx 7632a?mp3?03/06 timings table 275. external clock ac timings v dd = 1.65 to 3.6 v; t a = -40 to +85c waveforms figure 150. external clock waveform symbol parameter min max unit t clcl clock period 38 ns t chcx high time 10 ns t clcx low time 10 ns t clch rise time 3 ns t chcl fall time 3 ns t cr cyclic ratio in x2 mode 40 60 % t clcl v ih1 v il t chcx t clch t chcl t clcx
253 AT85C51SND3bx 7632a?mp3?03/06 ordering information table 280. ordering information notes: 1. codec option, see table 281 below. 2. contact sales office for availability. table 281. part number codec option table 282. part number information part number temp. range package packing product marking 85c51snd3b1n (1) -rttul industrial & green lqfp100 tray 85c51snd3b1n (1) -ul 85c51snd3b1n (1) -7ftul industrial & green ctbga100 (2) tray 85c51snd3b1n (1) -ul 85c51snd3b2n (1) -rttul industrial & green lqfp100 tray 85c51snd3b2n (1) -ul 85c51snd3b2n (1) -7ftul industrial & green ctbga100 (2) tray 85c51snd3b2n (1) -ul 85c51snd3b3n (1) -rttul industrial & green lqfp100 tray 85c51snd3b3n (1) -ul 85c51snd3b3n (1) -7ftul industrial & green ctbga100 (2) tray 85c51snd3b3n (1) -ul part number mp3 wma 85c51snd3bx00 no no 85c51snd3bx01 ye s no 85c51snd3bx02 no yes 85c51snd3bx03 ye s yes part number 1.8v dc-dc audio codec 85c51snd3b1 no no 85c51snd3b2 no yes 85c51snd3b3 ye s yes
254 AT85C51SND3bx 7632a?mp3?03/06 package information lqfp 100
255 AT85C51SND3bx 7632a?mp3?03/06 ctbga 100
1 7632a?mp3?03/06 AT85C51SND3a table of contents features ................................................................................................. 1 description ............................................................................................ 2 key features ......................................................................................... 2 block diagram ...................................................................................... 3 application information ....................................................................... 4 very low voltage 1.8v system ............................................................................ 4 low voltage 3v system........................................................................................ 5 pin description ..................................................................................... 6 pinouts.................................................................................................................. 6 signals description ............................................................................................... 7 internal pin structure ...........................................................................................15 power management ............................................................................ 18 power supply...................................................................................................... 18 power reduction mode ...................................................................................... 20 reset .................................................................................................................. 23 registers..............................................................................................................25 clock controller .................................................................................. 27 oscillator............................................................................................................. 27 clock generator.................................................................................................. 28 system clock generator..................................................................................... 29 dfc/nfc clock generator................................................................................. 30 mmc clock generator ........................................................................................ 31 sio clock generator .......................................................................................... 32 registers............................................................................................................. 33 special function registers ............................................................... 36 sfr pagination................................................................................................... 36 sfr registers .................................................................................................... 37 memory space .................................................................................... 49 memory segments.............................................................................................. 49 memory configuration ........................................................................................ 50 registers............................................................................................................. 51 interrupt system ................................................................................. 55 interrupt system priorities .................................................................................. 55 external interrupts .............................................................................................. 58
2 7632a?mp3?03/06 AT85C51SND3a registers..............................................................................................................59 timers/counters ................................................................................. 65 timer/counter operations .................................................................................. 65 timer clock controller ........................................................................................ 65 timer 0................................................................................................................ 66 timer 1................................................................................................................ 69 interrupt .............................................................................................................. 70 registers..............................................................................................................71 watchdog timer ................................................................................. 75 description.......................................................................................................... 75 clock controller .................................................................................................. 75 operation............................................................................................................ 76 registers..............................................................................................................77 data flow controller .......................................................................... 78 cpu interface ..................................................................................................... 78 clock unit ........................................................................................................... 78 data flow descriptor .......................................................................................... 78 crc processor................................................................................................... 79 null device.......................................................................................................... 79 channel priority .................................................................................................. 80 data flow status ................................................................................................ 80 data flow abort.................................................................................................. 80 data flow configuration ..................................................................................... 81 interrupts............................................................................................................. 81 registers............................................................................................................. 82 usb controller.................................................................................... 85 description.......................................................................................................... 85 general operating modes .................................................................................. 86 interrupts............................................................................................................. 87 power modes...................................................................................................... 88 speed control..................................................................................................... 89 memory access capability ................................................................................. 89 memory management......................................................................................... 90 pad suspend...................................................................................................... 91 otg timers customizing ................................................................................... 92 plug-in detection ................................................................................................. 92 id detection ........................................................................................................ 94 registers............................................................................................................. 94 usb software operating modes....................................................................... 100 usb device operating modes......................................................... 101 introduction ....................................................................................................... 101
3 7632a?mp3?03/06 AT85C51SND3a power-on and reset ........................................................................................ 101 speed identification .......................................................................................... 101 endpoint reset ................................................................................................. 102 usb reset........................................................................................................ 102 endpoint selection............................................................................................ 102 endpoint activation ........................................................................................... 103 address setup .................................................................................................. 103 suspend, wake-up and resume ..................................................................... 104 detach .............................................................................................................. 104 remote wake-up ............................................................................................. 105 stall request ................................................................................................ 105 control endpoint management ................................................................... 106 out endpoint management ............................................................................. 107 in endpoint management ................................................................................. 109 isochronous mode ............................................................................................ 112 overflow............................................................................................................ 112 interrupts........................................................................................................... 113 registers............................................................................................................115 usb host operating modes............................................................. 127 pipe description................................................................................................ 127 detach .............................................................................................................. 127 power-on and reset ......................................................................................... 127 device detection............................................................................................... 128 pipe selection................................................................................................... 128 pipe configuration .............................................................................................129 usb reset........................................................................................................ 130 address setup .................................................................................................. 130 remote wake-up detection ............................................................................. 130 usb pipe reset................................................................................................ 130 pipe data access ............................................................................................. 130 control pipe management ................................................................................ 130 out pipe management .................................................................................... 131 in pipe management ........................................................................................ 133 interrupt ............................................................................................................ 134 registers............................................................................................................136 audio controller ............................................................................... 149 clock generator................................................................................................ 149 audio processor ............................................................................................... 149 audio codec ......................................................................................................154 audio dac interface ......................................................................................... 156 registers........................................................................................................... 158 nand flash controller ...................................................................... 168 functional overview.......................................................................................... 168
4 7632a?mp3?03/06 AT85C51SND3a clock unit ......................................................................................................... 169 control unit....................................................................................................... 169 data unit........................................................................................................... 176 end of data transfer ........................................................................................ 179 security unit ..................................................................................................... 179 card unit........................................................................................................... 182 interrupt unit..................................................................................................... 183 registers........................................................................................................... 184 mmc/sd controller........................................................................... 191 clock generator................................................................................................ 191 command line controller................................................................................. 191 data line controller...........................................................................................194 card management ............................................................................................ 200 interrupt ............................................................................................................ 201 registers............................................................................................................202 parallel slave interface .................................................................... 207 description........................................................................................................ 207 interrupts........................................................................................................... 210 registers............................................................................................................211 serial i/o port.................................................................................... 213 description........................................................................................................ 213 baud rate generator........................................................................................ 215 receiver............................................................................................................ 217 transmitter........................................................................................................ 218 interrupts........................................................................................................... 218 registers........................................................................................................... 219 serial peripheral interface ............................................................... 223 description........................................................................................................ 224 interrupt ............................................................................................................ 230 registers........................................................................................................... 230 display interface............................................................................... 233 configuration .................................................................................................... 233 registers............................................................................................................236 keyboard interface ........................................................................... 239 description........................................................................................................ 239 registers........................................................................................................... 240 electrical characteristics ................................................................. 241 absolute maximum rating................................................................................ 241 dc characteristics............................................................................................ 241
5 7632a?mp3?03/06 AT85C51SND3a ac characteristics.............................................................................................246 ordering information........................................................................ 253 package information ........................................................................ 254 lqfp 100 ......................................................................................................... 254 ctbga 100 .......................................................................................................255
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